Chris Yates

Head of AI and Machine Learning, Thalia

Chris Yates, Vice President of Software Engineering, leads development of EDA software for analog and mixed-signal design, optimisation and technology migration. His work applies statistical methods, mathematical optimisation and AI and machine learning to automate performance tuning and preserve circuit intent across process nodes. With a background in statistics, mathematics and artificial intelligence, he focuses on reducing design iteration time while maintaining predictability and robustness in advanced AMS flows.

Marcel Ahmedzai

Application Engineer Architect, Cadence

Marcel Ahmedzai is an engineering architect at Cadence with a focus on mixed signal verification and is based in Bracknell, England. Prior to Cadence he was a CAD engineer at Mitel Semiconductor and Zarlink Semiconductor. Marcel has been with Cadence for over 20 years and has a bachelor’s degree in Mathematics from the University of Hertfordshire.

Mike Bartley

F0under and CEO, Alpinum

Mike started in software testing in 1988 after completing a PhD in Math, moving to semiconductor Design Verification (DV) in 1994, verifying designs (on Silicon and FPGA) going into commercial and safety-related sectors such as mobile phones, automotive, comms, cloud/data servers, and Artificial Intelligence. Mike built and managed state-of-the-art DV teams inside several companies, specialising in CPU verification.

Mike founded and grew a DV services company to 450+ engineers globally, successfully delivering services and solutions to over 50+ clients . The company was acquired by Tessolve Semiconductors in 2020 and Mike worked at Tessolve as SVP.

Mike started Alpinum in April 2025 to deliver a range of start-of-the art industry solutions.

Asad Ali

Senior IC Architect ‑ Analogue and Mixed Signal, Novomorphic

Asad Ali, Senior IC Architect at Novomorphic, champions a System First approach to analogue and mixed-signal development. He has held leadership roles at Maxim Integrated, OnSemi, Dialog Semiconductor and LSI Logic, leading the development of high-volume RFIC, power and mixed-signal IC products from concept to production.

Kostas Glaros

Associate Director – Analogue IC Design, Ensilica Plc

Kostas Glaros is an analogue/mixed-signal technical lead with EnSilica Plc. Over the past decade he has led teams bringing multiple mixed-signal ASICs from initial concept to mass production. He focuses on medical, automotive, and industrial control applications, and has a keen interest on design methodology and tools. Kostas holds a PhD in low-power medical electronics from Imperial College London.

Gautham Sathyan

Mixed Signal Modeling & Verification Engineer, Cirrus Logic

Gautham Sathyan is part of the Mixed-Signal Modeling and Verification group at Cirrus Logic in the Newbury office. His work spans a wide range of responsibilities, including early stage architectural modeling of mixed signal blocks, requirements definition, and establishing analog/digital boundary and the chip level schematic hierarchy. He is involved in netlisting and chip bring up DMS simulation, SystemVerilog real number modeling of low level analog cells, and to define and implement chip level AMS simulations.

With a background in analog design, Gautham particularly enjoys the challenges of modeling and debugging complex mixed signal systems. Outside of work, he spends most of his time running after his young children, though he hopes to one day start learning to play Indian music on the guitar.

Vladimir Zivkovic

Principal Product Engineer, Siemens EDA

Vladimir Zivkovic is a principal product engineer for Analog Mixed-Signal and Defect-oriented Test at Siemens EDA. He graduated from the Faculty of Electrical Engineering at the University of Nis in Former Yugoslavia and obtained PhD in Electrical Engineering from the University of Twente, the Netherlands.

He has more than 20 years of industrial experience in Mixed-signal DfT, test flow automation, test coverage analysis and AMS verification. His previous affiliations include Philips Research (Netherlands), NXP Semiconductors (Netherlands), D4T Systems (small startup company, Netherlands), Nikhef/CERN (Netherlands/Switzerland), Cadence Design Systems (Scotland, UK) and Infineon (Denmark). He is program committee member of IEEE European Test Symposium (ETS) and provided significant contribution during the development of IEEE 2427 standard for Analog Defect Modeling and Coverage. He is also vice chair of IEEE P1687.2 (Analog Test Access standardization) working group.

Bart Keppens

Chief Business Development, Sofics

Bart Keppens received an engineering degree in electronics in 1996 and started his career at imec in Belgium. From 2002 he joined Sarnoff Europe, solving on-chip ESD related problems for customers worldwide. After a management buy-out in June 2009, Sarnoff Europe became ‘SOFICS – Solutions for ICs’ where Bart is responsible for global business development. Bart (co-) authored more than 40 peer-reviewed published articles on ESD protection.

Lee Harrison

Director of Product Marketing, Tessent, Siemens EDA

Lee Harrison is Director, Product Marketing, with Siemens Tessent Division. He has over 25 years of industry experience working with Siemens Tessent DFT products, with a focus on safety and security. Lee Received his BEng in MicroElectronic Engineering from Brunel University London in 1996. Lee presents regularly at industry conferences such as DAC, ITC, VTS, ETS, and DATE.

Neel Goplan

Executive Director, Technical Product Management, Synopsys

Neel Gopalan is an Executive Director, in the Products and Market group. Neel leads Technical Product Management for AMS tools including Custom Compiler, PrimeSim and Characterization. Neel has been with Synopsys for the last 20 years; during this time he has been part of Custom Compiler Product Engineering team. He was an integral part of the team that built Custom Compiler along with all the collaterals needed for Custom Design. Neel and his team built industry’s 1st iPDK, which is now the standard for PDKs in the industry. Neel now leads Analog Design Migration, ASO and Layout Synthesis. Prior to Synopsys, Neel worked for Cadence for 5 years

Haydn Povey

Founder and CEO, SCI Semiconductor

With over 30 years experience in the technology domain Haydn has unparalleled experience in microprocessor IP, cyber security, and real world cyber-physical systems.

Having led the introduction of Arm Cortex-M processors he subsequently led the Processor Divisions security technologies, including TrustZone & SecurCore.

He is a founder board member of the IoT Security Foundation.

Dave Sanders

Associate Fellow, Rolls-Royce

Dave Sanders is an Associate Fellow at Rolls-Royce specialising in the development of complex electronic hardware. He has 28 years of experience working in the electronics industry, with 26 of those developing the safety critical microprocessors that form the heart of the Rolls-Royce control systems for both aerospace and non-aerospace applications.

Dave is a member of the European DO254 Users Group since 2012 and has contributed to various regulation working groups including co-authoring AMC 20-152A. He became a Fellow of the IET in 2018 and was awarded the Rolls-Royce Controls Gold Innovation Award in 2015 in recognition of the successful development of the sixth-generation safety critical microprocessor, which has already accumulated over 30 million fault free flying hours.

In his spare time, Dave is a keen runner and currently Lichfield Running Club Secretary.

Michael O’Sullivan

Engineering director, Cadence

Michael O’Sullivan is an engineering director at Cadence with a focus on verification and is based in Edinburgh, Scotland. Michael has been with Cadence for over 27 years with various roles in sales, marketing and design services.

Prior to Cadence he was a design engineer at S3 Group in Dublin, Ireland and at Philips in Eindhoven, The Netherlands. Michael has an Masters of Engineering Science from the National University of Ireland.

Loay Qteet

Staff Application Engineer, Synopsys

Loay Qteet, Applications Engineering, Staff Engineer at Synopsys, with six years of experience in the Electronic Design Automation (EDA) field. He specializes in physical design, RTLIIGDS flow development, and EDA applications of Implementation and AI. Loay has played a key role in supporting various customer, helping them to achieve their goals effectively and ensuring that Synopsys products meet their evolving requirements.

Catriona Wright

Co-founder, Chipletti

Catriona Wright is co-founder of Chipletti, a Cambridge-based fabless semiconductor startup developing AI accelerators for physical AI systems that require low power, high performance real-time operation within tight SWaP-C constraints. She works across strategy, partnerships, and operations while helping translate emerging AI compute needs into practical hardware solutions.

Matt Cossins

Ecosystem Development Manager, Arm

Matt Cossins is an Ecosystem Development Manager in Arm’s AI and Developer Platforms group, where he supports the adoption of Arm-powered AI compute platforms through developer education, enablement, and collaboration between industry and academia.

Raj Gawera

Chief Operating Officer, UK Semiconductor Centre

Raj has over 30 years of experience in the semiconductor field having held senior technical and commercial roles in semiconductor organisations spanning IP, Fabless and IDM business models. He is now COO of the newly formed UK Semiconductor Centre – with an ambitious plan to strengthen the UK semiconductor ecosystem and grow international partnerships.

Mahdieh Ghoddusi

Director of Delivery, UKESF

Prof. Nick McKeown