FPGA Frontrunners Event
April 16 @ 10:00 am - 2:30 pm
FPGA Frontrunner Event
Field Programmable Gate Arrays (FPGAs) play a critical role in modern electronic systems, powering applications that range from everyday consumer products to mission-critical infrastructure. Their ability to be customized and reconfigured after deployment makes them uniquely valuable in fast-moving technology environments. At the same time, this adaptability introduces distinct security challenges that must be carefully addressed.
Because FPGAs can be reprogrammed in the field, they present a broader attack surface than fixed-function hardware. Threats targeting configuration data, intellectual property, firmware integrity, and runtime behavior can compromise not only the device itself, but also the larger systems that rely on it. As FPGAs are increasingly used to support advanced workloads—including data-intensive and intelligent processing—security risks continue to grow in both scope and impact.
Effective FPGA security extends beyond physical protection. It encompasses the full lifecycle and ecosystem surrounding the device, including design tools, bitstreams, firmware, software interfaces, and data flows. In systems that incorporate adaptive or AI-assisted functionality, ensuring trust, integrity, and resilience across this ecosystem is especially critical.
This event explores the evolving landscape of FPGA security, highlighting emerging threats, recent advances, and proven mitigation strategies. Through expert insights and real-world case studies, the program aims to equip engineers, researchers, and security professionals with practical guidance for securing FPGA-based systems today and in
knowledge, techniques, and assurance frameworks necessary to design systems that are not only resilient and secure—but demonstrably so.
Who Should Attend
FPGA Designers and Engineers
System Architects
Safety and Security Specialists
Supply Chain Professionals
Industry Regulators and Standards Bodies
Why Attend?
- Gain insights from leading experts on the evolving risks and mitigation strategies
- Learn how to meet functional safety and security requirements across multiple industries
- Network with industry peers and potential collaborators
- Participate in discussions on best practices, regulatory trends, and real-world case studies
Outline Agenda
| Time | Details |
|---|---|
| 10:00 | Registration |
| 10:30 | Microchip Secure FPGA’s Ian Pearson Pr. ESE, Microchip |
| 11:00 | A Visual Demonstration of True Random Numbers from a Quantum Computer Phill J Payne Principal Digital Design Engineer, Novomorphic |
| 11:30 | Are FPGAs unique for security? Martin Thompson Senior Technical Specialist, ZF Engineering Solutions |
| 12:00 | Beyond Bitstream Encryption: FPGA Security for High-Assurance Systems Daniel Tee Senior Firmware (FPGA) Engineer, Leonardo |
| 12:30 | Networking Lunch |
| 13:30 | Overview of prEN50767 : CRA Vertical Standard for FPGA/ASIC Peter Trott Staff FAE, Microchip |
| 14:00 | Hardware-Rooted Bitstream Security Mans Ahmadian Chief Innovation Officer, Sundance |
| 14:30 | Wrap Up |
| 14:45 | Close |
Phill J Payne, Principal Digital Design Engineer, Novomorphic
Presentation: A Visual Demonstration of True Random Numbers from a Quantum Computer
True randomness is one of those things everyone assumes they have… right up until security, trust, or assurance actually matters.
This session reveals a practical way to pull physical entropy from a real quantum computer and inject it into FPGA and embedded systems as a usable, engineering-grade input. You’ll see quantum behaviour turned into something tangible and immediate — a live “quantum dice” demonstrator that makes the invisible visible — and you’ll learn why this matters far beyond novelty.
We’ll explore what changes when your randomness isn’t “noisy enough” pseudo-random, but rooted in genuine physical uncertainty, and how that can reshape thinking around key generation, nonces, reseeding, and trusted system design. A live comparison between simulation and real quantum hardware draws a clear line between “looks random” and “is random”.
If you build secure edge systems and care about trust boundaries, this will change how you think about entropy.
Martin Thompson, Senior Technical Specialist, ZF Engineering Solutions
Presentation: Are FPGAs unique for security?
In this talk we will investigate the degree to which systems containing programmable logic (including FPGAs) can be considered “unique” in their security requirements and implementation options, when compared to more conventional microcontroller and desktop processor systems.
We will briefly define what we mean by “security” in this context (both in terms of market requirements and attacker motivations) and what primitives can be used to achieve it. A review of the variety of potential attacks will be presented and we will spend some time on the peculiarities of FPGA-based systems by comparing them directly with other implementation strategies. Finally, we will conclude with an answer to the question posed in the title.
Mans Ahmadian, Chief Innovation Officer, Sundance
Presentation: Hardware-Rooted Bitstream Security and Secure Manufacturing Workflow
A Defense-Grade Implementation Using PolarFire FPGA on Sundance PCIe104N Platform As FPGAs become central to mission-critical defense and aerospace systems, the security challenge has shifted. It is no longer enough to protect configuration data in the fi eld; we must also secure it during manufacturing, programming, testing, and across the entire supply chain. When production is distributed across multiple facilities and third-party partners, the FPGA bitstream becomes a high-value target, vulnerable to interception, overbuilding, hardware substitution, or reverse engineering. This talk presents a defence-grade secure provisioning workflow implemented on the Sundance PCIe104N platform, built around the PolarFire MPF500T FPGA, and explains how it establishes trust from silicon to system deployment.
Daniel Tee, Senior Firmware (FPGA) Engineer, Leonardo
Presentation: Beyond Bitstream Encryption: FPGA Security for High-Assurance Systems
Field programmable gate arrays (FPGAs) are increasingly deployed in systems where failure or compromise is not an option – from defence and aerospace to critical infrastructure and advanced industrial platforms. In these high assurance environments, security requirements extend beyond the protections normally offered by device vendors. Engineers must consider the broader context of threats, deployment conditions, and system level risk.
Ian Pearson, Pr. ESE, Microchip Technology Inc.
Presentation: Leveraging Microchip Secure FPGAs
The foundation of a secure end product lies in the right choice of components. CRA requires a ‘Secure by Design’ approach to product development and support throughout the lifecycle. Microchip FPGA’s have a long history of secure FPGA’s designed to meet the most demanding of military applications but available to all
Peter Trott, Staff FAE, Microchip Technology Inc.
Presentation: Overview of prEN50767 : CRA Vertical Standard for FPGA/ASIC
The EU CRA requirements can be met via a presumption of conformity using horizontal and vertical harmonised standards. These standards are in development and will release very close to the enforcement date. In this session we will give some insight into what is coming in the vertical standard for FPGA/ASIC. The prEN50767 standard provides the requirements for FPGA/ASIC vendors to meet the Important Class I categorisation of FPGA/ASIC in the EU CRA.
