Conference Report

Trends in Semiconductor Systems Design

6th February 2025  |   Reading

The DESN: Trends in Semiconductor System Design event, held on Thursday, 6 February 2025 in Reading, UK, brought together key figures from across the semiconductor industry to explore the latest innovations and challenges shaping modern system-on-chip (SoC) design. Hosted by the UK’s Design and Embedded Systems Network (DESN), the event focused heavily on how artificial intelligence and machine learning (AI/ML) are transforming semiconductor workflows—from IP development to chip packaging, validation, and sign-off.

A major theme was the integration of AI into EDA (Electronic Design Automation) tools, with companies like Synopsys, Siemens EDA, and Cadence demonstrating how generative AI is accelerating chip design, reducing manual work, and improving productivity. Synopsys, for example, showcased its AI-driven design platform, capable of automating up to 70% of mobile SoC design tasks. However, several speakers also cautioned about AI “hallucinations” and stressed the importance of building trustworthy, secure AI models tailored for critical design environments.

Another focal point was the shift towards chiplet-based architectures and advanced packaging technologies. Speakers from Arm, CSA Catapult, and imec Cambridge discussed how traditional scaling is becoming increasingly difficult, pushing the industry to explore modular chip designs. These approaches offer new levels of scalability and flexibility but also introduce challenges in terms of integration, testing, and yield optimization.

The event also highlighted the growing complexity of verification and validation. Engineers are facing tighter timelines and rising demands for functional safety, especially in AI workloads and edge applications. Presentations emphasized the need for more intelligent test strategies and AI-augmented verification flows. Overall, the event painted a clear picture: the semiconductor design world is undergoing rapid transformation, with AI and modular design at the core of the next generation of innovation.

Unlocking the AI advantage with Siemens EDA products

This video showcases how Siemens EDA is strategically deploying AI to address the escalating challenges in semiconductor design, such as increasing complexity, soaring costs (up to $320-400 million for a latest node chip), and the significant talent shortage (projected 40,000 engineers short).

Siemens views AI as a crucial methodology to enhance design productivity, with internal studies showing up to 50% average productivity gains when using AI-enhanced flows.

Their approach is centered on “production-grade AI,” adhering to five key principles: verifiability (showing proof of work), usability (easy to use without requiring a PhD), generality (working across the entire design spectrum), robustness (consistent answers), and foundational accuracy and reliability. Siemens integrates analytical, predictive, and generative AI across its product portfolio.

Practical applications include using AI for early power analysis and modeling during software development, a 3D-IC design space optimization platform (Innovator 3D-IC), optimizing transistor cells (STO Cell Optimizer), automating neural network model translation to silicon via high-level synthesis (Catapult AI neural network), optimizing place and route for PPA targets, analyzing spice parameters, and introducing NLP (Natural Language Processing) interfaces to tools to simplify complex tasks and assist with rule decks, assertions, and documentation.

Siemens also uses AI to reduce debug time (e.g., 15x faster with Calibre products) and optimize test processes (e.g., 5x reduction in test time with Tessent). Ultimately, all products within Siemens EDA are increasingly incorporating some form of AI to bring significant productivity gains and ensure “right-first-time” silicon

Driving Advancements in Semiconductor Technology

This video features a Bruno Jansen from IMEC, a leading research institute with 40 years of experience in technology scaling and semiconductor innovation. IMEC acts as a bridge between the corporate and academic worlds, maintaining significant capital investment, including ASML equipment, to drive its research. It has over 6,000 employees and close to a billion euros in revenue.

Here’s a summary of the key points discussed:

IMEC’s UK Presence: IMEC has established a growing entity in Cambridge, UK, to leverage the region’s resources and foster collaborations, particularly benefiting from the wider pool of talent available compared to its Leuven base. They aim to enable collaboration, work with UK companies strong in fab, and support startups.

Driving Technology Roadmaps: IMEC has driven the technology roadmap for over 40 years and plans to continue for decades. Current production is around 2-3 nanometers, with research in nano sheets and development of PDKs widely used in the industry. A significant challenge is the density problem, particularly impacting SRAM scaling, leading to research into alternative memory types like M1 STM1 and SOT.

System Technology Co-Optimization (STCO): IMEC is focusing on STCO, which involves the ability to combine underlying semiconductor technologies (like scaling and memory roadmaps) with system-level design. This new approach for IMEC allows insights from system design to influence technology roadmaps and vice versa, aiming for increased performance, reduced cost, and lower power.

From Chip to Systems

This video, featuring Paul Jarvie from CSA Catapult, a government-funded entity, discusses the evolving landscape of semiconductor packaging and integration, shifting from “chip to systems”.

With Moore’s Law facing increasing challenges and design costs soaring for advanced nodes, the focus is now on advanced hybrid integration, including 2.5D and 3D packaging, and co-packaged optics to enhance performance and power efficiency.

The speaker emphasizes that packaging is no longer a post-design add-on but a central hub in co-design methodologies, requiring deep understanding from wafer fab to post-fab processes.

The talk also highlights the critical need to integrate diverse materials like compound semiconductors with silicon for applications ranging from power to photonics, and how AI is becoming instrumental for multi-objective optimization to quickly find optimal packaging solutions.

This future demands multi-disciplinary engineers capable of addressing complex thermal management, interconnects, and reliability to ensure “right-first-time” silicon

AI & the Verification Engineer

This video, “Trends in Semiconductor Design – AI & the Verification Engineer,” features Andrew Bond discussing the impact of Artificial Intelligence (AI) on the semiconductor design and verification industry.

Andrew shares personal insights from 25 years of experience in processes and System-on-Chips (SOCs), including 17 tape-outs, emphasizing that the views expressed are personal and not on behalf of their company

Overall Outlook: Trust But Verify: AI won’t replace people but will accelerate innovation, leading to higher quality verification or shorter time scales (more right-first-time silicon). Engineers will shift focus from memorizing syntax to clearly explaining intent and organizing data/code.

The semiconductor industry, being small, needs to embrace software design styles for AI relevance. The speaker uses AI constantly, noting significant personal productivity improvement. He suggests an opportunity to move towards Python-based verification (e.g., cocotb, Verilator) due to Python’s richer language features, libraries, and better AI support, potentially saving substantial development time.

Crucially, while AI can produce amazing results (like a perfect FIFO), it can also be “incredibly wrong” and stubborn, so “Trust but Verify” is paramount to avoid “colossal coughs” (major mistakes