Introduction to Semiconductor Design Verification (DV)

By the end of the course, participants should be able to

1. Describe the best-practice DV strategies applied currently to semiconductor digital designs
2. Understand the main methodologies, tools and languages used in those best-practice DV strategies
3. Apply those DV methodologies, tools and languages to basic digital designs at IP and subsystem level
4. Analyse a “real” semiconductor digital design (IP and subsystem) and suggest an appropriate DV strategy
5. Understand best-practice DV so they can discuss DV topics confidently with colleagues
6. Have sufficient understanding of DV tools and methodologies to contribute effectively to real projects

For more information on the course, check out the video here: https://www.youtube.com/watch?v=Y5E3YDXMQgI

The course runs for 5 weeks with the following main activities. Details are given using the links.

• the course runs for 2 weeks with 2 hours of lecture/practical per day. There are 20 1-hour sessions split between:
  • lectures covering the major DV topics (including UVM and OSVVM/UVVM)
  • practical sessions helping students through all the major concepts, SV/VHDL, UVM and OSVVM/UVVM for writing their own test benches
  • sessions on debug (details).
• A large database of design and verification examples and exercises (including UVM and OSVVM/UVVM) graded as 3 distinct levels of difficulty and complexity ready for running on a wide variety of simulators (details).
  • These can download these so participants can run them on their machines using their licenses.
• A number of pre-recorded videos (details) covering running the exercises and using various EDA tools.
• Use of a FIFO example that builds through the course to show a full end-to-end example of verification.
• Use of Moodle (details) for testing understanding of the course content and tracking progress on the course
• Details of the 20 sessions
  • Lecture: “Introduction”, “Simulation-based Verification”
  • Practical: “Introduction to the exercises”
  • Lecture:  “Stimulus generation”
  • Practical: “Introduction to Verilog/SV/VHDL and simulation” “Running directed test benches”
  • Lecture: “Checking and Assertion-Based-Verification”
  • Practical: ”Verification checkers and assertions”
  • Lecture: “Coverage”
  • Practical: “Coverage”
  • Lecture: “The FIFO example”
  • Practical: “FIFO IP verification
  • Lecture: “Introduction to UVM”
  • Practical: “UVM”
  • Lecture: Introduction to OSVVM
  • Practical: OSVVM
  • Lecture: “Further UVM”
  • Practical: “Advanced UVM”
  • Lecture: “Introduction to debug”, “Making debug efficient and effective”, “Additional topics”
  • Practical: “Debug and qualification for IP verification”
  • Lecture: “The Verification Cycle”, “IP, subsystem and SoC”
  • Practical: “FIFO subsystem verification”
  • Lecture: ““Verification in practise”,
  • Practical: “CPU-based SoC verification”
  • Lecture: Summary

There are no pre-requisites, although some experience of programming (preferably with an Object-Oriented language) would be useful. The course is suitable for a wide range of people working in semiconductor design and development, especially recent graduates.

The TechWorks Academy present the course to introduce participants to DV.

The course runs from Jan 29th to Feb 9th . We also welcome new additions such as the Feature Extraction and Automation/AI Course. The new RiscV Verification course to be added soon.

1. University students going on or started a placement at a semiconductor design company
2. Design engineers wanting to learn more about verification and/or how to write re-usable verification IP
3. University graduates starting or started work at a semiconductor design company
4. Engineers wanting to transition their career to or are just curious about DV
5. Managers wanting some understanding of the topic

• Member = £1200 per delegate

Valid to any TechWorks community member*

• Non-member = £1500 per delegate

The Design Verification course (delivered by TechWorks Academy) met our main objective which was to upskill our graduate engineers to have the knowledge and understanding of the application of VHDL and OSVVM in verification environments, the course also covered SV and UVM. Course understanding was helped with the extensive set of examples and exercises which allowed the participants to progress from initially simple, to complex design and test benches – which included debug and fix.

The flexible delivery and timing of the course allowed participants to continue working on their own assigned projects during the training. We did not have to assign internal senior engineers to support the upskilling of these engineers.

The course was delivered by a very senior presenter with over 30 years’ experience in Design Verification. He was able to provide valuable insights into the practicalities of verifying real designs and was very responsive to participant questions, taking time outside of the online sessions to give individual support.

After the 1^st run and full delivery of the course, the organiser took extensive feedback from all participants which has now been incorporated into the next course. The next course will start on February 7^th and we have already registered 8 participants for this.

Pete Leonard, Electronics Design Manager, Group Engineering, Renishaw