Events
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Synopsys: Exploring a Software First Approach to Avoid SoC Re-spins
Traditional coverage-based verification methods are no longer sufficient to verify complex SoCs integrating many processor cores and IP subsystems. In this Synopsys webinar we will cover the primary pre-silicon methods, along with their benefits, to execute a software first strategy.
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Synopsys: 3DIC Design from Concept to Silicon
This webinar will outline the different market trends for 3DIC designs and explain how designers can maintain such new trends to deliver their designs with optimized latency, power, performance, and area.
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Commodity Codes and Import Declarations
On January 1st 2022, two changes came into effect that importers and exporters should be aware of.
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Cadence TECHTALK Series: Adopting a Faster, More Efficient Path to Multi-Chiplet Design
Webinar with dates running between 23rd February and 6th April
With the increasing popularity of multi-chiplet designs that address Moore’s law slowdown and reticle size limitations, leading foundries are offering multiple advanced packaging and die stacking options for different applications. -
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Rules of Origin when exporting to the EU
Where your product comes from or is made, can have a huge impact on the tariffs applicable when selling to another country. Ensuring your goods comply with the rules of origin in the EU/UK Trade & Cooperation Agreement is essential for you to export your product smoothly and avoid costly errors.
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Synopsys: Early and Accelerated SoC Connectivity Verification using VC Formal Connectivity Checking App
Complex bus protocols, increased on-chip functionalities, coupled with limited shared I/O resources, result in complex wiring connections in SoCs with numerous muxing schemes.
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Technology Start-Up Event
The first of these events organized by Silicon Catalyst UK and NMI is focused on the "Forming semiconductor start-ups" stage.
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FPGA Frontrunner Meet & Greet
NMI is all about sharing knowledge and creating communities. The FPGA Front Runners exists to share knowledge, best practice and to create a community around FPGAs and ASIC development.
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Designing the future: Tackling design challenges through collaboration
Hilton London Olympia 380 Kensington High St, LondonThis launch event will define new collaborative groups to address shared challenges and opportunities.