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SUMMARY:IMAPS-UK: MicroTech 2026 Conference
DESCRIPTION:IMAPS-UK: MicroTech 2026 ConferenceREGISTERIMAPS-UK: MicroTech 2026 Conference at King’s Conference Centre\, Hedge End\, Southampton – Thursday 26th March 2026 and Heterogeneous Integration – Explained! Workshop at University of Southampton on Wednesday 25 March 2026 \nThe IMAPS-UK MicroTech 2026 Conference on Thursday 26th March 2026 at the King’s Conference Centre\, Hedge End\, Southampton will focus on Driving Innovation in Semiconductor Packaging. The preliminary Conference Agenda includes state-of-the-art presentations on the advanced packaging market\, the UK Semiconductor Centre\, advanced packaging technologies including laser based processes\, heterogeneous integration\, interposers and 3D integration. \nMore Information and Registration: https://www.imaps.org.uk/events/microtech-2026-driving-innovation-in-semiconductor-packaging/ \nThe Conference is complemented by a Workshop on Heterogeneous Integration – Explained! On Wednesday 25th March 2026 at the University of Southampton. \nMore Information and Registration: https://www.imaps.org.uk/events/heterogeneous-integration-electronics/ \nPlease contact the IMAPS-UK Office (office@imaps.org.uk ) with any questions.
URL:https://desn.org.uk/event/imaps-uk-microtech-2026-conference/
LOCATION:Southampton
CATEGORIES:DESN Promoted Event
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SUMMARY:Designing the Future: Analogue Mixed Signal (AMS)
DESCRIPTION:Designing the Future: Analogue Mixed Signal (AMS)Jump to SpeakersJump to AgendaREGISTERAs complexity accelerates\, designers face growing challenges in architecture\, design\, system scaling and workflow.  \nFollowing our Digital Design event in November\, this next event brings together Analogue and Mixed Signal chip architects and designers to explore real-world pain points and application trends. During the day\, we will hear from experts about the challenges and opportunities facing industry and identify how\, by working together\, we can support industry growth.  \nThe event is structured around three contemporary themes\, with a plenary discussion after each to discuss the topics raised and identify relevant actions going forward.  \nRunning concurrently at the same venue\, TechWorks and UKESF are hosting a Chip Design Early Careers event to bring together industry and emerging talent. The UKESF Digital Design – Early Careers track\, will give companies the opportunity to engage with up to 50 next-generation chip designers (students and graduates) at the point where they are making career choices. Participants can speak directly to these early-career engineers who are keen to learn about a career in chip design\, and which organisations they can join and grow with.  \nOverview  \n\nThe future of AMS Design\n\nHow is AMS design evolving and where are we compared with pure-play digital CMOS  \n\nDesign for performance\, noise\, and integrity across PVT \nTrade-offs across process nodes and scaling limits; voltage\, noise\, performance\, cost \nDesign migration\, IP integration and reuse \nDesign flow and productivity: How can automation and AI help? \nLayout challenges\, routing\, optimization and physical verification \nCo-simulation\, model abstraction and system-level verification \n\n\nSystem architecture and Integration\n\nMeeting system requirements while avoiding parasitics and interference is not just a circuit-level challenge. What are the current trends in system architecture and integration? \n\nSystem partitioning\, simulation and integration: Performance / Power / Area \nDigital-analogue interfacing and interconnect. Interference mitigation and isolation \nMulti-die integration: Yield reliability\, Power delivery\, Thermal management \nSignal integrity and noise coupling in advanced packaging\, 2.5D and 3D \nMulti-die mixed signal chiplets and heterogeneous integration \n\n\nApplication drivers for AMS Design\n\nMany emerging technologies are driving AMS innovation. What are the major application challenges pushing the frontier of analogue design today? \n\nFuture compute and AI \nHigh-speed SerDes\, Photonic interconnect\, Clock & data recovery \nPower delivery\, voltage regulation and monitoring \nAnalog and in-memory compute \nIoT\, connectivity\, med-tech and wearables \nLow-noise analogue sensor integration / Energy harvesting \nPhysical AI / Neuromorphic compute \nLow power RF \n\nAGENDA \n\n\n\n\nTIME\nDETAILS\n\n\n\n\n09:15\nRegistration\n\n\n10:00\nTechWorks DESN Introduction – Scene setting & objectives\nJillian Hughes\, Head of Semiconductors\, DESN & Charles Sturman\, CEO\, TechWorks\n\n\n\nThe Future of AMS Design\nHow is AMS design evolving and where are we compared with pure-play digital CMOS\n\n\n10:10\nSystem-First Design for High-Performance Mixed-Signal\nAsad Ali\, Senior IC Architect\, Novamorphic\n\n\n10:30\nBridging the Verification Gap Between Digital and Analog IC Design \nMarcel Ahmedzai\, Application Engineer Architect\, Cadence\n\n\n10:50\nTop‑Down Approach to Mixed‑Signal Verification\nGautham Sathyan\, Mixed Signal Modeling & Verification Engineer\, Cirrus Logic\n\n\n11:10\nVerifying AMS Designs\nMike Bartley\, CEO\, Alpinum\n\n\n11:30\nDiscussion and CTA\n\n\n11:55\nSponsor talk: Lee Harrison\, Director of Product Marketing\, Tessent\, Siemens EDA\n\n\n12:00\nNetworking Lunch\n\n\n\nSystem architecture and Integration\nMeeting system requirements while avoiding parasitics and interference is not just a circuit-level challenge. What are the current trends in system architecture and integration?\n\n\n13:00\nStructured AMS migration: Device-level validation to layout closure with intelligent automation\nChris Yates\, Head of AI and Machine Learning\, Thalia\n\n\n13:20\nRevolutionizing Analog Layout Synthesis through GenAI and Machine Learning Technologies\nNeel Goplan\, Executive Director\, Technical Product Management\n\n\n13:40\nBeyond 1.8 V: Enabling Robust 3.3 V Interfaces in 28 nm CMOS and 7 nm FinFET with Overvoltage Tolerant Specialty I/Os\nBart Keppens\, Chief Business Development\, Sofics\n\n\n14:00\nDiscussion & Call to Action\n\n\n14:25\nBreak\n\n\n\nApplication drivers for AMS Design\nMany emerging technologies are driving AMS innovation. What are the major application challenges pushing the frontier of analogue design today?\n\n\n15:10\nAMS from beamforming arrays to safety critical ASICs\nKonstantinos Glaros\, Associate Director – Analogue IC Design\, Ensilica Plc\n\n\n15:20\nAnalog Scan: A new frontier for Mixed-signal test\nVladimir Zivkovic\, Principal Product Engineer\, Siemens EDA\n\n\n15:40\nDiscussion & Call to Action\n\n\n16:05\nRefreshments and Networking\n\n\n17:00\nClose\n\n\n\n\nAGENDA \n\n\n\n\n09:15\nRegistration\n\n\n10:00\nTechWorks DESN Introduction – Scene setting & objectives\nJillian Hughes\, Head of Semiconductors\, DESN & Charles Sturman\, CEO\, TechWorks\n\n\nThe Future of AMS Design\nHow is AMS design evolving and where are we compared with pure-play digital CMOS\n\n\n10:10\nSystem-First Design for High-Performance Mixed-Signal\nAsad Ali\, Senior IC Architect\, Novamorphic\n\n\n10:30\nBridging the Verification Gap Between Digital and Analog IC Design\nMarcel Ahmedzai\, Application Engineer Architect\, Cadence\n\n\n10:50\nTop‑Down Approach to Mixed‑Signal Verification\nGautham Sathyan\, Mixed Signal Modeling & Verification Engineer\, Cirrus Logic\n\n\n11:10\nVerifying AMS Designs\nMike Bartley\, CEO\, Alpinum\n\n\n11:30\nDiscussion and CTA\n\n\n11:55\nSponsor talk: Lee Harrison\, Director of Product Marketing\, Tessent\, Siemens EDA\n\n\n12:00\nNetworking Lunch\n\n\nSystem architecture and Integration\nMeeting system requirements while avoiding parasitics and interference is not just a circuit-level challenge. What are the current trends in system architecture and integration?\n\n\n13:00\nStructured AMS migration: Device-level validation to layout closure with intelligent automation\nChris Yates\, Head of AI and Machine Learning\, Thalia\n\n\n13:20\nRevolutionizing Analog Layout Synthesis through GenAI and Machine Learning Technologies\nNeel Goplan\, Executive Director\, Technical Product Management\n\n\n13:40\nBeyond 1.8 V: Enabling Robust 3.3 V Interfaces in 28 nm CMOS and 7 nm FinFET with Overvoltage Tolerant Specialty I/Os\nBart Keppens\, Chief Business Development\, Sofics\n\n\n14:00\nDiscussion & Call to Action\n\n\n14:25\nBreak\n\n\nApplication drivers for AMS Design\nMany emerging technologies are driving AMS innovation. What are the major application challenges pushing the frontier of analogue design today?\n\n\n15:00\nAMS from beamforming arrays to safety critical ASICs\nKonstantinos Glaros\, Associate Director – Analogue IC Design\, Ensilica Plc\n\n\n15:20\nAnalog Scan: A new frontier for Mixed-signal test\nVladimir Zivkovic\, Principal Product Engineer\, Siemens EDA\n\n\n15:40\nDiscussion & Call to Action\n\n\n16:05\nRefreshments and Networking\n\n\n17:00\nClose\n\n\n\n\nAMS SpeakersChris Yates\nHead of AI and Machine Learning\, Thalia \nChris Yates\, Vice President of Software Engineering\, leads development of EDA software for analog and mixed-signal design\, optimisation and technology migration. His work applies statistical methods\, mathematical optimisation and AI and machine learning to automate performance tuning and preserve circuit intent across process nodes. With a background in statistics\, mathematics and artificial intelligence\, he focuses on reducing design iteration time while maintaining predictability and robustness in advanced AMS flows. \nPresentation×Structured AMS migration: Device-level validation to layout closure with intelligent automation\nAnalog and mixed signal IP migration using manual or in-house methods is rarely optimal and often slow and difficult. Y et migration remains necessary due to commercial and technical pressures. This session outlines practical ways to make migration predictable and efficient\, including automated device-level comparison\, early PPA assessment and intelligent layout adaptation. Drawing on recent project experience with machine learning-enhanced tools\, it demonstrates how AMS engineers can preserve performance while establishing a repeatable migration methodology. The approach combines traditional analog expertise with selective automation to reduce iteration cycles and improve reliability. The discussion will show where intelligent tools can augment\, not replace\, engineering judgment in critical design decisions. \nCloseMarcel Ahmedzai\nApplication Engineer Architect\, Cadence \nMarcel Ahmedzai is an engineering architect at Cadence with a focus on mixed signal verification and is based in Bracknell\, England. Prior to Cadence he was a CAD engineer at Mitel Semiconductor and Zarlink Semiconductor. Marcel has been with Cadence for over 20 years and has a bachelor’s degree in Mathematics from the University of Hertfordshire. \nPresentation×Bridging the Verification Gap Between Digital and Analog IC Design\nAs transistor geometries continue to shrink\, modern integrated circuit designs face escalating complexity that challenges the effectiveness and efficiency of traditional verification practices. Even at the block level\, the functional checks required to ensure correct behavior demand substantial time and resources\, and this burden increases dramatically when scaling to chip‑level and system‑level verification. In digital design\, these challenges have long been addressed through established verification methodologies\, dedicated verification engineers\, and standardized frameworks such as UVM. In contrast\, analog and mixed‑signal (AMS) design teams often lack a comparable verification mindset\, leading to late discovery of bugs\, costly respins\, and delays in time‑to‑market. This paper outlines the requirements and methodologies needed to elevate AMS verification to the maturity of its digital counterpart. By examining current gaps\, resource impacts\, and emerging best practices\, we provide a structured view of how systematic AMS verification can significantly reduce design risk and improve overall product quality. \nCloseMike Bartley\nF0under and CEO\, Alpinum \nMike started in software testing in 1988 after completing a PhD in Math\, moving to semiconductor Design Verification (DV) in 1994\, verifying designs (on Silicon and FPGA) going into commercial and safety-related sectors such as mobile phones\, automotive\, comms\, cloud/data servers\, and Artificial Intelligence. Mike built and managed state-of-the-art DV teams inside several companies\, specialising in CPU verification. \nMike founded and grew a DV services company to 450+ engineers globally\, successfully delivering services and solutions to over 50+ clients . The company was acquired by Tessolve Semiconductors in 2020 and Mike worked at Tessolve as SVP. \nMike started Alpinum in April 2025 to deliver a range of start-of-the art industry solutions. \nPresentation×Verifying AMS Designs\nWe will be investigating strategies for verifying AMS designs from test planning\, through test bench design and bring up\, to test generation\, closure and signoff. The talk will focus on practical\, best-practice verification solutions for a variety of designs\, so that the delegates can take away ideas that they can start using immediately. \nCloseAsad Ali\nSenior IC Architect ‑ Analogue and Mixed Signal\, Novomorphic \nAsad Ali\, Senior IC Architect at Novomorphic\, champions a System First approach to analogue and mixed-signal development. He has held leadership roles at Maxim Integrated\, OnSemi\, Dialog Semiconductor and LSI Logic\, leading the development of high-volume RFIC\, power and mixed-signal IC products from concept to production. \nPresentation×System-First Design for High-Performance Mixed-Signal\nIn modern mixed-signal systems\, the analog figure-of-merit (FOM)\, capturing the signal-to-noise ratio (SNR) delivered per unit power over a defined bandwidth\, is a key determinant of overall system efficiency. As CMOS technology continues to scale\, reduced intrinsic gain\, lower supply voltages\, and increased variability are fundamentally limiting the ability of traditional analog design techniques to sustain competitive FOM\, directly impacting power budgets\, performance headroom\, and implementation cost. \nThis talk reframes the problem from a circuit-centric challenge to a system-level opportunity – a System First Approach. Rather than relying solely on device-level optimisation\, we examine architectural and system-partitioning strategies that shift performance dependencies. \nWe present practical\, system-driven design methodologies that mitigate technology-imposed analog limitations\, enabling next-generation mixed-signal platforms to achieve aggressive performance targets while improving power efficiency\, scalability\, and time-to-market in line with Power-Performance-Cost objectives. \nCloseKostas Glaros\nAssociate Director – Analogue IC Design\, Ensilica Plc \nKostas Glaros is an analogue/mixed-signal technical lead with EnSilica Plc. Over the past decade he has led teams bringing multiple mixed-signal ASICs from initial concept to mass production. He focuses on medical\, automotive\, and industrial control applications\, and has a keen interest on design methodology and tools. Kostas holds a PhD in low-power medical electronics from Imperial College London. \nPresentation×AMS from beamforming arrays to safety critical ASICs\nIn large\, multi-channel SoCs\, AMS verification is essential for validating the integration of multiple analogue channels operating concurrently alongside complex digital signal processing. Safety-critical ASICs\, such as industrial and automotive controllers\, demand demonstrable vertical integration and traceable compliance with requirements. This talk discusses examples of AMS and DMS verification in such applications and some associated challenges. \nCloseGautham Sathyan\nMixed Signal Modeling & Verification Engineer\, Cirrus Logic \nGautham Sathyan is part of the Mixed-Signal Modeling and Verification group at Cirrus Logic in the Newbury office. His work spans a wide range of responsibilities\, including early stage architectural modeling of mixed signal blocks\, requirements definition\, and establishing analog/digital boundary and the chip level schematic hierarchy. He is involved in netlisting and chip bring up DMS simulation\, SystemVerilog real number modeling of low level analog cells\, and to define and implement chip level AMS simulations. \nWith a background in analog design\, Gautham particularly enjoys the challenges of modeling and debugging complex mixed signal systems. Outside of work\, he spends most of his time running after his young children\, though he hopes to one day start learning to play Indian music on the guitar. \n×Top‑Down Approach to Mixed‑Signal Verification\nA framework for first‑silicon success \nSilicon Respins and late surprises can feel inevitable on complex mixed‑signal ASICs\, especially when sophisticated digital control meets rich analog content. They needn’t be\, argues Gautham Sathyan\, in this fast‑paced\, practitioner‑focused talk as he lays out a concrete framework combining a top‑down\, model‑driven verification methodology with tight cross‑team alignment and disciplined use of AMS co‑simulation. 3 key CTAs from this talk : \n\nModel early\, verify continuously.\nCo‑sim sparingly\, where it counts.\nShip together\, not in silos.\n\nClosePresentationVladimir Zivkovic\nPrincipal Product Engineer\, Siemens EDA \nVladimir Zivkovic is a principal product engineer for Analog Mixed-Signal and Defect-oriented Test at Siemens EDA. He graduated from the Faculty of Electrical Engineering at the University of Nis in Former Yugoslavia and obtained PhD in Electrical Engineering from the University of Twente\, the Netherlands. \nHe has more than 20 years of industrial experience in Mixed-signal DfT\, test flow automation\, test coverage analysis and AMS verification. His previous affiliations include Philips Research (Netherlands)\, NXP Semiconductors (Netherlands)\, D4T Systems (small startup company\, Netherlands)\, Nikhef/CERN (Netherlands/Switzerland)\, Cadence Design Systems (Scotland\, UK) and Infineon (Denmark). He is program committee member of IEEE European Test Symposium (ETS) and provided significant contribution during the development of IEEE 2427 standard for Analog Defect Modeling and Coverage. He is also vice chair of IEEE P1687.2 (Analog Test Access standardization) working group. \nPresentation×Analog Scan: A new frontier for Mixed-signal test\nDeveloping tests for designs with mixed-signal circuits has always been a bottleneck during IC product sign-off\, regardless of the application. This talk presents a revolutionary approach for creating efficient manufacturing mixed-signal tests that reduce test costs and test escapes. The methodology is called analog scan and requires DfT of a circuit-under-test (CUT) to inject stimulus signals and observe responses. The inserted circuitry is not placed in series with signal propagation paths\, and it is turned off in the mission mode. The control and output of the DfT circuitry is connected to test data registers (TDRs)\, typically placed outside the mixed-signal block under test. \nAnalog scan methodology brings multiple benefits. First\, there is a massive decrease of test cost\, since analog scan tests run orders of magnitude faster than a large majority of spec-based tests on ATE. Analog defect simulation also runs much faster than for spec-based tests. With appropriate automation\, top-level test development is also significantly accelerated. Defect coverage figures achieved with analog scan are usually higher than those obtained with functional tests. Lastly\, analog scan facilitates diagnosis of field returns. \nBart Keppens\nChief Business Development\, Sofics \nBart Keppens received an engineering degree in electronics in 1996 and started his career at imec in Belgium. From 2002 he joined Sarnoff Europe\, solving on-chip ESD related problems for customers worldwide. After a management buy-out in June 2009\, Sarnoff Europe became ‘SOFICS – Solutions for ICs’ where Bart is responsible for global business development. Bart (co-) authored more than 40 peer-reviewed published articles on ESD protection. \nPresentation×Beyond 1.8 V: Enabling Robust 3.3 V Interfaces in 28 nm CMOS and 7 nm FinFET with Overvoltage Tolerant Specialty I/Os\nAs CMOS nodes scale\, designers face a widening gap between core capabilities and system-level requirements. While foundry GPIOs in FinFET and GAA processes typically top out at 1.8V\, many applications still demand 3.3V “Over-Voltage Tolerant” (OVT) interfaces for legacy compatibility and robust system integration. Conversely\, the rise of chiplet architectures introduces the opposite challenge: Die-to-Die (D2D) interfaces that must operate at specialty voltages below the typical GPIO range (1V or lower) to minimize power and maximize speed. \nThis presentation explores the design and ESD protection of these specialty interfaces. We examine the “3.3V in a 1.8V process” dilemma\, focusing on stacking techniques to maintain Safe Operating Area (SOA) during power sequencing and transient events. We then pivot to the unique requirements of chiplet interconnects. Unlike standard I/Os\, D2D interfaces require: (a) Specialized ESD: Traditional >2kV HBM protection is often overkill for D2D\, introducing excessive parasitic capacitance that limits bandwidth. (b) Thin-Oxide Integration: To achieve high speeds\, D2D circuits utilize sensitive thin-oxide transistors that are easily damaged without custom ESD clamps. (c) Area Efficiency: With thousands of required connections\, standard I/O pads consume prohibitive silicon area. \nAttendees will gain a practical framework for specifying and verifying both higher and lower voltage specialty I/Os\, with an emphasis on co-designing circuits and ESD to optimize PPA in modern\, heterogeneous systems. \nLee Harrison\nDirector of Product Marketing\, Tessent\, Siemens EDA \nLee Harrison is Director\, Product Marketing\, with Siemens Tessent Division. He has over 25 years of industry experience working with Siemens Tessent DFT products\, with a focus on safety and security. Lee Received his BEng in MicroElectronic Engineering from Brunel University London in 1996. Lee presents regularly at industry conferences such as DAC\, ITC\, VTS\, ETS\, and DATE. \nNeel Goplan\nExecutive Director\, Technical Product Management\, Synopsys \nNeel Gopalan is an Executive Director\, in the Products and Market group. Neel leads Technical Product Management for AMS tools including Custom Compiler\, PrimeSim and Characterization. Neel has been with Synopsys for the last 20 years; during this time he has been part of Custom Compiler Product Engineering team. He was an integral part of the team that built Custom Compiler along with all the collaterals needed for Custom Design. Neel and his team built industry’s 1st iPDK\, which is now the standard for PDKs in the industry. Neel now leads Analog Design Migration\, ASO and Layout Synthesis. Prior to Synopsys\, Neel worked for Cadence for 5 years \nPresentation×Revolutionizing Analog Layout Synthesis through GenAI and Machine Learning Technologies\nThe rapid advancement of semiconductor technology necessitates innovative approaches to Analog Layout Synthesis\, a critical aspect in circuit design for FinFET and GAA nodes. This presentation introduces Industry’s First transformative potential of Generative AI (GenAI) and Machine Learning (ML) in automating and optimizing the analog layout process. We will discuss how GenAI can generate high-quality layout designs by learning from vast datasets of existing designs\, while ML algorithms enhance the efficiency of design creation and predictions. Furthermore\, we will delve into the role of AI in facilitating intelligent decision-making throughout the design process\, enabling adaptive responses to design constraints and objectives. By integrating these cutting-edge technologies\, we aim to significantly reduce design time\, improve layout quality\, and foster innovation in analog circuit design. This presentation will provide insights into the methodologies employed\, the challenges encountered\, and the future directions of analog layout synthesis in the context of AI-driven advancements \n×Meet the Students\n\nFrom RTL and verification to open-source silicon tapeouts\, these exceptional students are already making an impact in digital chip design \n James Ashie Kotey | Electronics & Computer Engineering\, University of Sheffield | IC Engineering Intern at EnSilica \nJames has contributed to commercial ASIC projects in RTL design and functional verification\, and has led three open-source silicon projects from concept to tapeout using open-source EDA tools and PDKs. \nCarys MacIntyre | Robotics Engineering (Integrated Master’s)\, University of Bath | Hardware Intern at Siemens EDA (Tessent Embedded Analytics) \nCurrently on a 12-month placement in digital RTL verification\, Carys is gaining hands-on verification experience alongside her master’s studies. \nCharlie Teare | Mechatronics & Robotic Systems (BEng with Year in Industry) \, University of Liverpool \nFollowing a placement with EnSilica’s digital design team\, Charlie continues collaborating with industry while completing his final year project focused on a fabric/interconnect generator. \nRonit Ravi | Electronic Engineering\, Imperial College London \nNow in his final year\, Ronit previously completed a placement in Design Verification at Siemens EDA and continues to collaborate during his master’s research. \nThis event provides students and early-career designers with direct exposure to professionals in digital chip design \,  embedding their learning and offering tangible inspiration for careers in the UK semiconductor sector. \n\nDigital Design Early Careers SpeakersHaydn Povey\nFounder and CEO\, SCI Semiconductor \nWith over 30 years experience in the technology domain Haydn has unparalleled experience in microprocessor IP\, cyber security\, and real world cyber-physical systems. \nHaving led the introduction of Arm Cortex-M processors he subsequently led the Processor Divisions security technologies\, including TrustZone & SecurCore. \nHe is a founder board member of the IoT Security Foundation. \nDave Sanders\nAssociate Fellow\, Rolls-Royce \nDave Sanders is an Associate Fellow at Rolls-Royce specialising in the development of complex electronic hardware. He has 28 years of experience working in the electronics industry\, with 26 of those developing the safety critical microprocessors that form the heart of the Rolls-Royce control systems for both aerospace and non-aerospace applications. \nDave is a member of the European DO254 Users Group since 2012 and has contributed to various regulation working groups including co-authoring AMC 20-152A. He became a Fellow of the IET in 2018 and was awarded the Rolls-Royce Controls Gold Innovation Award in 2015 in recognition of the successful development of the sixth-generation safety critical microprocessor\, which has already accumulated over 30 million fault free flying hours. \nIn his spare time\, Dave is a keen runner and currently Lichfield Running Club Secretary. \nMichael O’Sullivan\nEngineering director\, Cadence \nMichael O’Sullivan is an engineering director at Cadence with a focus on verification and is based in Edinburgh\, Scotland. Michael has been with Cadence for over 27 years with various roles in sales\, marketing and design services. \nPrior to Cadence he was a design engineer at S3 Group in Dublin\, Ireland and at Philips in Eindhoven\, The Netherlands. Michael has an Masters of Engineering Science from the National University of Ireland. \nLoay Qteet\nStaff Application Engineer\, Synopsys \nLoay Qteet\, Applications Engineering\, Staff Engineer at Synopsys\, with six years of experience in the Electronic Design Automation (EDA) field. He specializes in physical design\, RTLIIGDS flow development\, and EDA applications of Implementation and AI. Loay has played a key role in supporting various customer\, helping them to achieve their goals effectively and ensuring that Synopsys products meet their evolving requirements. \nCatriona Wright\nCo-founder\, Chipletti \nCatriona Wright is co-founder of Chipletti\, a Cambridge-based fabless semiconductor startup developing AI accelerators for physical AI systems that require low power\, high performance real-time operation within tight SWaP-C constraints. She works across strategy\, partnerships\, and operations while helping translate emerging AI compute needs into practical hardware solutions. \nRead More \nCatriona has more than 25 years of experience delivering complex semiconductor products from concept through to production. Her career spans digital design\, program leadership\, and scaling multidisciplinary teams to deliver advanced silicon. Before founding Chipletti\, she held roles at both start-ups and large companies including Riverlane\, DisplayLink\, Cambridge Semiconductor\, TTPCom and Nortel Networks\, leading IC development programmes and coordinating cross-functional engineering teams. \nShe holds a First Class MEng in Electrical and Electronic Engineering from the University of Edinburgh and an MBA from The Open University. Catriona is passionate about building strong deep tech teams and helping grow the semiconductor ecosystem in the UK. She is also active in outreach\, running coding clubs for primary school students and encouraging more young people – particularly girls – to explore engineering. \n\n\nModerator \n\nMatt Cossins\nEcosystem Development Manager\, Arm \nMatt Cossins is an Ecosystem Development Manager in Arm’s AI and Developer Platforms group\, where he supports the adoption of Arm-powered AI compute platforms through developer education\, enablement\, and collaboration between industry and academia. \nRead More \nAn alumnus of the UKESF programme\, he holds an MEng in Electrical and Electronic Engineering from the University of Nottingham\, where his thesis focused on neuromorphic AI. He previously held engineering roles at Capgemini\, delivering software and embedded research projects for multiple clients\, and at Cambridge-based cellXica\, where he worked on embedded and RTL design for software-defined radio in 5G communications. \nMatt is a recipient of awards from organisations including the IET\, UKESF\, and Electronics Weekly\, and mentors engineering students through the Arkwright Scholarships Trust. \n\nRaj Gawera\nChief Operating Officer\, UK Semiconductor Centre \nRaj has over 30 years of experience in the semiconductor field having held senior technical and commercial roles in semiconductor organisations spanning IP\, Fabless and IDM business models. He is now COO of the newly formed UK Semiconductor Centre – with an ambitious plan to strengthen the UK semiconductor ecosystem and grow international partnerships. \nRead More \nIn his early career\, Raj was part of initial IEEE 802.11 team to define first WLAN standard in 1996 – a technology which has now shipped many billions of units. Raj also helped pioneer the first 3G data transmissions working with Motorola and others to demonstrate one of the first 3G video calls at the 3GSM show in 1998 – many years before 3G licences were awarded. \nRaj was a founder member of 3G technology startup UbiNetics (1999)\, that successfully exited in 2005 for over $120m USD. As part of that deal\, Raj joined CSR and ultimately took the role of VP Marketing where he was part of the team that acquired SiRF Technologies for $136m (2009) to add GPS technology to CSR portfolio. In 2012\, he helped sell CSR’s handset business to Samsung in a deal worth $310m for 310 staff. As part of Samsung\, Raj was promoted to VP heading up the SCSC division leading the silicon and software development for Samsung’s chipsets for over a decade\, providing connectivity technology that shipped in hundreds of millions of Samsung products. \nRaj has held a number of board positions including Chair of Cambridge Wireless and NED for CSA Catapult bringing experience and advice on the global semiconductor market. \n\nMahdieh Ghoddusi\nDirector of Delivery\, UKESF \nMahdieh Ghoddusi\nDirector of Delivery\, UKESF \nProf. Nick McKeown
URL:https://desn.org.uk/event/designing-the-future-analogue-mixed-signal-ams/
LOCATION:Regents University London\, Inner Circle\, Regent’s Park\, London\, NW1 4NS
CATEGORIES:DESN Event
ATTACH;FMTTYPE=image/jpeg:https://desn.org.uk/wp-content/uploads/2026/01/Featured-Image-2026-03-03T103724.942.jpg
END:VEVENT
END:VCALENDAR