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DTSTART;TZID=Europe/London:20251106T090000
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DTSTAMP:20260119T093201Z
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UID:23065-1762419600-1762450200@desn.org.uk
SUMMARY:Designing the future: Tackling design challenges through collaboration
DESCRIPTION:REGISTERThank you to our Sponsors:  IC Resources   |    Synopsys   |   Cadence\nWomen in Techworks Sponsor: MicroTECH\nTechWorks DESN network aims to support the UK chip design industry by building communities of shared interest. This launch event will define new collaborative groups to address shared challenges and opportunities.\nAs chip complexity continues to accelerate\, designers face growing challenges in architecture design\, system scaling & integration and workflow. This hands-on event brings together chip architects\, designers and engineers to explore real-world pain points and application trends\, sharing lessons learned. The objective is to build ongoing collaboration supporting industry growth. \nWe will explore three contemporary themes during the event\, with a plenary discussion following each one to discuss the topics raised and identify relevant actions and initiatives for DESN to curate going forward. \nOUTLINE AGENDA \n\n\n\n\n\nTIME\nDETAILS\n\n\n\n\n09:00\nRegistration\n\n\n10:00\nTechWorks DESN Introduction – Scene setting and objectives\n\n\n10:10\nTHEME: The Future of Digital Design \nAs product roadmaps grow more demanding\, the design challenges are intensifying. How are chip designs evolving architecture\, workflow and methodology to stay ahead of the curve? \n\nNigel Toon\, Executive Chairman and co-founder\, Graphcore) \nMark Zwolinski\, Professor\, University of Southampton\n\n\n\n\n11:00\nDiscussion and CTA\n\n\n12:00\nNetworking Lunch\n\n\n13:00\nTHEME: Addressing the Chiplet Challenge \nTo achieve vendor and substrate-independent multi-die chiplet systems\, the industry must align on physical\, thermal\, and electrical compatibility\, adopt standard packaging techniques\, and develop sustainable business models. How can we make this a reality? \n\nYiru Zhong\, Market Development Specialist\, Arm\nPrashant Dubey\, Path Finding Researcher\, Imec Cambridge UK\nJohn Goodenough\, Professor of Microelectronic Systems\, University of Sheffield\n\n\n\n\n14:20\nDiscussion and CTA\n\n\n14:50\nBreak\n\n\n15:00\nTHEME: Applications of Digital Design \nMultiple breakthrough techniques are being driven by innovations in chip design. How can designers continue to deliver these market specific roadmaps at pace – from AI and intelligent mobility to high-performance\, energy-efficient computing. \n\nDorian Haci\, CEO and co-founder\, MintNeuro\nDr Jeremy Bennett\, Founder and Chief Executive\, Embecosm\n\n\n\n\n14:10\nDiscussion and CTA\n\n\n16:40\nRefreshments and Networking\n\n\n17:30\nClose\n\n\n\n\nNigel Toon\nExecutive Chairman and co-founder\, Graphcore \nNigel is a leading AI entrepreneur and is the founder and CEO of Graphcore.ai.  He sits as a Non-Executive Director on the board of UK Research and Innovation and sat on the UK Prime Minister’s Business Council. He has been recognized with numerous industry awards\, being ranked #1 on Business Insider’s UK Tech 100 and named as one of the ‘Top 100 entrepreneurs in the UK’ by the Financial Times. He was awarded a Doctor of Science degree from the University of Bristol and is the author of the best-selling book How AI Thinks. \nYiru Zhong\nMarket Development Specialist\, Arm \nWith more than twenty-five years in the technology sector\, Yiru Zhong has led market development for emerging technologies. Yiru’s work spans product strategy\, go-to-market design\, and partner development\, consistently aligning engineering roadmaps with market signals and operational execution. Having experienced through cycles of booms and busts in the last two decades\, Yiru brings disciplined judgment about what scales and what does not.\nYiru approaches innovation from the perspective of adoption: who will use it\, why it matters\, and how value is realised across ecosystems. This orientation enables clear separation of durable demand from transient hype. Drawing on professional and personal experience across Asia and Europe\, Yiru bridges diverse customer requirements\, regulatory contexts\, and supply chains to translate technical potential into commercial outcomes. \nDorian Haci\nCEO & Co-Founder\, MintNeuro \nDr Dorian Haci is an entrepreneur\, engineer and researcher with over a decade of experience in academia and industry. As CEO and Co-Founder of MintNeuro\, a spinout from Imperial College London\, he is pioneering the next generation of neural implants through innovative semiconductor technologies that enable safer\, smarter and more scalable brain interfaces. He also serves as an Enterprise Fellow at the Royal Academy of Engineering and a Visiting Researcher at Imperial\, where he earned his PhD in microelectronics for implantable medical devices. Under his leadership\, MintNeuro has secured multi-million-pound funding from the UK’s NIHR\, ARIA and Innovate UK to support R&D collaborations with world-leading research institutes and medical device companies. His work focuses on advancing chip-based solutions for neurological conditions such as epilepsy\, Parkinson’s and dementia. \nABSTRACT×When Chips meet the Brain: designing the next generation of neural interfaces\nDigital technology has evolved through successive generations of interfaces. Mainframes brought computing into institutions\, personal computers to the desk\, smartphones to the hand\, and wearables to the body – each step enabled by advances in semiconductor design. A similar path has shaped implantable medical technology. Early pacemakers and open-loop stimulators evolved into sensory prostheses and adaptive neuromodulators\, reflecting the same semiconductor progress from transistors to integrated circuits\, ASICs\, and systems-on-chip. \nWe are now entering a 5th generation where these trajectories converge. Neural interfaces are beginning to restore communication\, independence\, and quality of life for people with neurological conditions\, while opening new possibilities for interaction between humans and technology. Implantable systems face demanding requirements: they must be miniaturised\, ultra-low-power\, biocompatible\, hermetically sealed\, and reliable for years within a biological environment. Meeting these challenges depends on semiconductors that integrate multiple functions within millimetre-scale platforms. This requires new materials\, heterogeneous integration\, new architectures and computing paradigms for adaptive\, closed-loop operation. \nAt MintNeuro\, we develop semiconductor technology specifically for neural implants. Our purpose-build chip platform provides modular building blocks for functions like sensing\, stimulation\, and processing\, enabling medical device companies and researcher to design smaller\, safer\, and scalable systems. By co-designing chips and devices with academic and industrial collaborators\, we aim to bridge electronics and biology through shared design and engineering. This convergence defines a new frontier for semiconductor design – one where performance\, safety\, and collaboration meet. \nJohn Goodenough\nProfessor of Microelectronic Systems\, University of Sheffield \nInspiring the next generation of talented microelectronic system design engineers\, researchers and educators. Driving new programs in research and curriculum that address technology and skills gaps in the Semiconductor Industry. Focus areas on the architecture\, integration automation and assurance of secure\, power-efficient integrated semiconductor systems. \nPreviously\, experienced Global Technology Executive\, Systems and SoC Solutions architect. With broad view across multiple Information Technology\, Secure Distributed Embedded Systems\, System on Chip (SoC) and Electronic Design Automation. \nDr Jeremy Bennett\nFounder and Chief Executive\, Embecosm \nEmbecosm was founded in 2008 by Dr Jeremy Bennett\, an expert on hardware modeling and embedded software development. Previously Dr Bennett was Vice President of ARC International plc\, following their acquisition of Tenison Design where he had been CEO and CTO. \nDr Bennett is author of the popular textbook\, “Introduction to Compiling Techniques” (McGraw-Hill 1990\, 1995\, 2003) and holds an MA and PhD in Computer Science from Cambridge University. \nMark Zwolinski\nProfessor\, University of Southampton \nMark Zwolinski is a Professor in the School of Electronics and Computer Science\, University of Southampton. He has published over 220 journal and conference papers and 3 books. He has supervised 39 PhD students to completion. \nHis research interests include systems modelling\, design for reliability\, and heterogeneous computing. He is an Associate Editor of IEEE Transactions on VLSI. He has served on the programme committees of DATE\, DAC\, CODES+ISSS and ETS. He has also contributed to IEEE standards in test\, VHDL and Verilog. \nMark Zwolinski is a Fellow of the IET and BCS\, and a senior member of IEEE and ACM. He is a member of the Academic Accreditation Committee of the IET. \nABSTRACT×Adiabatic Logic Design for Low-Cost\, Low-Energy Processing\nFlexible electronics\, fabricated using\, for example\, Thin-Film Transistors (TFTs) are a promising technology for applications such as AI/ML at the edge. Such technologies often only implement N-type transistors and thus require pull-up logic\, which is very inefficient in terms of energy. \nAdiabatic logic was proposed as a low power technology several decades ago. The underlying principle is that logic gates should only be turned on as they are needed and not turned off when they are active. This is achieved by using the clock\, or multiple clock phases\, as the power supply for logic gates. Adiabatic logic designs have been proposed that use both NMOS and PMOS transistors\, but designs that use only NMOS transistors are possible. In order to achieve the promised energy efficiency\, however\, such circuits are very slow compared with modern CMOS technologies\, which means that adiabatic logic has never achieved widespread acceptance. On the other hand\, modern flexible electronics operate at relatively low frequencies. Thus\, adiabatic logic may prove to be an appropriate technique for low power design in these technologies. \nIn this talk we will look at how adiabatic logic can be implemented in an N-type technology. We will look at some circuit designs and show that the energy-efficient clock speeds of adiabatic logic are compatible with the clock speeds achievable in flexible electronics. Nevertheless\, formidable design challenges exist. Existing design tools are not compatible with adiabatic design styles. Signal paths need to be carefully balanced in order that the correct clock phases activate logic in sequence. In principle\, some energy recovery is possible in adiabatic circuits\, but we need to consider on-chip energy storage. \nPeter Birch\nHardware Lead Engineer\, Fractile \nPeter Birch is a Hardware Lead Engineer at Fractile\, working in the silicon team to deliver industry leading throughput and efficiency for AI inference workloads. Through past experience at VyperCore and Graphcore\, he has worked with cutting-edge approaches to design\, verification\, and infrastructure and advocates for the use of open source tooling and methodologies in commercial ASIC development. \nPrashant Dubey\nPath Finding Researcher\, Imec Cambridge UK \nPrashant Dubey is a pathfinding researcher at Imec Cambridge UK\, where he is engaged in STCO on 2nm nanosheets/forksheets and CFETS. This involves 3D and wafer level integration of TByte scale SRAMs\, integrated buck converters for high voltage to low voltage vertical power delivery\, back-side clock generation and routing and high-speed interconnects (petabytes/sec)\, for AI driven HP Compute in Data-Center applications. Prashant received his BE degree from Gorakhpur University\, India in 1998 and MS research degree from IIT Delhi\, on hyper-coupled ring oscillators. From 1998 to 2012 he worked for STMicroelectronics India as a Senior Design Expert\, Analog & RF\, where he designed embedded SRAMs and ROMs\, memory and SoC DFT\, analog and digital integer-N and fractional PLLs and oscillators. From 2012 to 2017 he worked for Synopsys India and led the research on low voltage SRAM architectures in 16-7nm FinFETs on write/read assist. From 2017 to 2018 he worked with Xilinx India on 3D FPGA architectures and in 2018\, joined ARM Cambridge UK and then MediaTek UK where he worked on voltage droop mitigation sensors and 5G mmW\, sub-100fs integrated jitter PLLs with dead-zone less 1st-order noise-shaped TDC architecture. He has produced\, 25 US Patents and 14 IEEE publications. \nABSTRACT×Collaborative Ecosystem as a key enabler of AI Driven Wafer Scale Data-Centres Research\nAt IMEC Cambridge UK\, we are currently involved in the pathfinding research of the xTCO in the domain of AI workload driven compute systems. Next-generation systems will need to handle AI models with over 100 trillion parameters or more\, driving an exponential increase in compute capacity demand. The power requirements of these systems are skyrocketing. Data centres consume between 2% and 3% of the world’s electricity (approx. 400 Terawatts)\, according to the International Energy Agency. AI enabling data-centres can consume a massive power of at least 500MW which is enough electricity to supply two million homes. As put forth by Feryal Clark\, Minister for AI\, “Just like coal and steam powered our past\, AI is powering the future. A significant portion of this energy is consumed by the data movement between isolated racks within data centres. Wafer-scale compute (WFC) aims to reduce this power consumption by integrating and packing compute and memory elements as close as possible. The key integration challenges in a WFC are driven by embedded memories which can be an SRAM\, DRAM or any other form of emerging memories\, in the orders of Terabytes\, achieving latencies in the order of Petabytes/second\, power delivery through vertical power delivery systems at high voltages with 500V to 1V integrated voltage converters in the order of 5 to 10Watts/mm2 and thermal extraction of a similar order. Advanced packaging is therefore another challenge due to heterogeneous integration of chiplets\, which involves advanced materials and their fusion with silicon e.g. Glass\, GaN etc. and is now playing a critical role in system design. Apart from advanced materials\, advanced packaging also involves new technologies like TSVs and hybrid bonding and their associated modelling for design co-optimization. IMEC pathfinding research has played a vital role in advancing the industry leading technology roadmap e.g. Gate-All-Around transistors\, Back-Side power delivery and continues to do so atleast with a decade margin between the conception and the productization. To convert brilliant but challenging ideas into successful products\, collaborative framework is pivotal at Imec. Imec Cambridge UK has been established to enable such a collaborative framework with UK Academia\, Start-ups and Industries to enable AI workload driven compute system. Our talk is aimed at the audience who are facing similar challenges in the field of wafer scale compute and see a value addition in such a collaborative framework with Imec.
URL:https://desn.org.uk/event/designing-the-future-tackling-design-challenges-through-collaboration/
LOCATION:Hilton London Olympia\, 380 Kensington High St\, London\, W14 8NL
CATEGORIES:Past Event
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