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DTSTART;VALUE=DATE:20250701
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SUMMARY:Verification Futures 2025 - FEATURING tracks from DESN and TechWorks AI
DESCRIPTION:Verification Futures 2025RegisterJoin us at the verification futures event taking place on 1st July 2025 in Reading.\nAs part of the expanded agenda for Verification Futures UK 2025\, a brand-new Design Track will debut\, hosted by the connected networks of Techworks (Techworks AI and DESN). This track will focus on the latest advances in AI-enabled IP\, next-generation SoC and semiconductor design\, and breakthrough technologies transforming the electronics landscape. \nThe Verification Futures conference has always provided a unique blend of presentations\, exhibitions\, and industry networking — offering a platform for end-users to define verification challenges and collaborate with engineers and vendors to create solutions. In 2025\, Verification Futures UK is expanding to reflect the evolving landscape of semiconductor design\, with a strong focus on AI/ML applications in IP/SoC\, FPGA\, and Mixed Signal designs. \nAttendees will gain access to cutting-edge technical content and expert presentations in \n• AI-Enhanced Semiconductor and IP Design\n• Next-Generation IP Architectures and Verification Strategies\n• Innovative Design Methodologies and Flows\n• Emerging and Breakthrough Technologies\n• Design for AI/ML Acceleration and Edge Computing< \nWhy Attend the Design Track? \n• Gain technical insights from industry-leading engineers\, architects\, and researchers\n• Learn from cutting-edge research and case studies addressing real-world design and verification challenges\n• Network with 250+ onsite professionals and 1\,000+ virtual participants across the semiconductor and verification ecosystem\n• Engage with emerging talent from the UK Electronics Skills Foundation (UKESF) showcasing their work\n• Collaborate with UK’s leading semiconductor startups through SiCatalyst UK\n• Be inspired by keynote addresses from visionaries\, including Sean Redmond \n \n\nDesign Track Agenda \n\n\n\nTime\nName\nTalk Title\n\n\n\n\n11:30\nMartin Zeller\, Dream Chip\nThree approaches to cope with rising ASIC complexity\n\n\n11:50\nGareth Richards\, Techworks\nTechWorks-AI and TAIBOM – Engineering Trustable AI\n\n\n12:10\nJames Lewis\, Red Semiconductor\nRISC-V: Innovating Within An Established Architecture\n\n\nBreak\n\n\n\n\n13:30\nBradley Geden\nThe Era of Agentic Engineering – Roadmap to Level 5\n\n\n14:00\nJohn Wickerson\, Imperial College London\nTesting and verifying the tools of hardware design\n\n\n14:20\nDoug Carsen\n\n\n\n14:40\nSpeaker TBC\n\n\n\n15:00\nSpeaker TBC\n\n\n\n15:20\nCristian Sestito\, University of Edinburgh\nTrIM: An Efficient Systolic Array for Convolutional Neural Networks\n\n\n15:40\nSpeaker TBC\n\n\n\n\n\n\nIntroducing New Tracks! \nVerification Futures 2025 will feature exciting new additions: \n• IP Stream: Explore the latest trends and solutions in intellectual property (IP) verification.\n• FPGA Track: Explore FPGA verification techniques\n• Mixed Signal\n• Verification Projects using Open Source/License-Free Tools \nRegistration \nRegister now to become a part of this event in-person or online. \n Click here to register.  \nTesting and verifying the tools of hardware design\nJohn Wickerson\, Senior Lecturer\, Imperial College London \nHardware engineers rely on several tools to build hardware\, such as high-level synthesis tools to convert C code into Verilog\, logic synthesis tools to convert Verilog into netlists\, and so on until they end up with a design that can be implemented on an FPGA or fabricated on an ASIC. Mistakes are difficult and expensive to rectify\, so engineers routinely use formal equivalence checkers to double-check that each transformation is correct. All these tools are critical pieces of software infrastructure and are highly trusted… but are they trustworthy? At Imperial\, we have been developing new techniques for testing and verifying hardware design tools. We have found bugs in all of the tools we have tested\, even the formal equivalence checkers. Some of these bugs cause the tools simply to crash; others are more sinister\, causing the tools to produce incorrect results. We are also prototyping new hardware design tools that come with a mechanically checked proof of their own correctness and thus promise the highest standard of reliability. The work is led by my current and former PhD students Yann Herklotz\, Quentin Corradi\, and Michalis Pardalos\, and is also in collaboration with George Constantinides\, Alastair Donaldson\, Emiliano Morini\, and Laura Pozzi. \nBiography \nJohn Wickerson is a Senior Lecturer in the Department of Electrical and Electronic Engineering at Imperial College London. His research is at the intersection of programming languages and hardware design \nTechWorks-AI and TAIBOM – Engineering Trustable AI\nGareth Richards\, Network Manager\, TechWorks AI \nOutline of the new Techworks-AI community\, bringing together members\, regardless of sector of operation\, who have a common interest in AI/ML technology\, developments and applications and an overview of the TAIBOM. \nBiography \nGareth has over 35 years’ experience leading the design and development of electronic systems used by millions of people every day in the UK\, United States and Japan\, including highly secure EAL4+ point of sale products used \nTesting and verifying the tools of hardware design\nJohn Wickerson\, Imperial College London \nHardware engineers rely on several tools to build hardware\, such as high-level synthesis tools to convert C code into Verilog\, logic synthesis tools to convert Verilog into netlists\, and so on until they end up with a design that can be implemented on an FPGA or fabricated on an ASIC. Mistakes are difficult and expensive to rectify\, so engineers routinely use formal equivalence checkers to double-check that each transformation is correct. All these tools are critical pieces of software infrastructure and are highly trusted… but are they trustworthy? At Imperial\, we have been developing new techniques for testing and verifying hardware design tools. We have found bugs in all of the tools we have tested\, even the formal equivalence checkers. Some of these bugs cause the tools simply to crash; others are more sinister\, causing the tools to produce incorrect results. We are also prototyping new hardware design tools that come with a mechanically checked proof of their own correctness and thus promise the highest standard of reliability. The work is led by my current and former PhD students Yann Herklotz\, Quentin Corradi\, and Michalis Pardalos\, and is also in collaboration with George Constantinides\, Alastair Donaldson\, Emiliano Morini\, and Laura Pozzi. \nBiography \nJohn Wickerson is a Senior Lecturer in the Department of Electrical and Electronic Engineering at Imperial College London. His research is at the intersection of programming languages and hardware design \nRethinking chip(let) design for next generation ADAS applications \nMartin Zeller\, Dream Chip \nThree approaches to cope with rising ASIC complexity. \nBiography \nMartin is responsible for the SoC development at Dreamchip\, a Tessolve company. \nHe has a diploma in electrical engineering from Leibniz University of Hannover and a business diploma from the University of Hagen. For more than 25 years he has developed ASICs and architectures\, mainly for video coding and imaging; starting with Infineon’s first mobile phone camera\, later enhancing Silicon Image’s HDMI interface ASICs to TV processor SoCs. In the last years he mainly worked on latest generation ADAS SoCs for several major players in the automotive industry. \nIn 2010 Martin joined DreamChip Technologies GmbH as the Head of SoC Design. In 2016 his team designed the world’s first 22nm ADAS SoC based on ARM’s Cortex A53 application processor and ARM’s Cortex R5 lockstep safety core as a platform for further developments. In the last years\, several automotive SoCs based on this platform have been built by Dreamchip. \nIn 2022 and 2023 new generations of Dreamchip’s platform have been taped out. \nMartin also worked as a trainer for ARM Cortex processor integration. \nThe Era of Agentic Engineering – Roadmap to Level 5\nBradley Geden\, Synopsys \nWe are now in the era of pervasive intelligence from voice assistants\, advanced robotics\, drone-based delivery to autonomous cars\, and chatbots. This begs the question\, how are we doing in design verification? Design verification is one of the most expensive and time-consuming activities for any chip design. Moreover\, every year the cost of design verification grows exponentially and despite that ½ of design re-spins are caused by functional or logic bugs. \nWith the advent of Large Language Models (LLM) and Generative Pre-Trained Transformer (GPT) models\, what are the possibilities in design verification? \nIn this session we will discuss the vision and roadmap of applying AI/ML to chip design and verification from what exists today to the “science fiction” future of Generative AI agents working together and orchestrated to design\, verify and debug designs under the guidance of human engineers to further drive innovation beyond what we can imagine today. \nBiography \nBradley Geden is the Senior Director of Product Management for Verification Software at Synopsys based in Sunnyvale\, CA. He has over 20 years of experience in the EDA industry covering a broad range of domains from Custom Design\, Circuit Simulation\, Digital Implementation and Verification in both Product Management and Sales Roles at Synopsys and Siemens EDA. Prior to entering the world of EDA he was an Analog Mixed-Signal Design Engineer working on Energy Measurement and Wireless Communication Chips. In his spare time\, Bradley enjoys travelling and exploring the world with his wife\, preferably on a sail boat! \nIn this session we will discuss the vision and roadmap of applying AI/ML to chip design and verification from what exists today to the “science fiction” future of Generative AI agents working together and orchestrated to design\, verify and debug designs under the guidance of human engineers to further drive innovation beyond what we can imagine today. \nPre-silicon Identification of Security Vulnerabilities\nDoug Carson\, Keysight Technologies \nCyber physical systems are dependent on a secure root of trust in silicon to ensure that hackers with physical access cannot gain control of the device or access critical data. The silicon powering these devices is delivered through a complex global supply chain which presents numerous opportunities for security vulnerabilities to be introduced at every stage in the lifecycle. In this talk we will begin with the motives for hacking hardware and how adversaries use side channel leakage and fault injection to exploit device vulnerabilities. We will then explore how these vulnerabilities can be detected at RTL and netlist levels to perform pre-silicon risk analysis. Lastly\, we will outline what countermeasures can be deployed at the design stage to resilience to hardware attacks. \nBiography \nDoug Carson is a device security solution expert working in Edinburgh on hardware security test solutions for the Keysight Device Security Lab. During his career he as architected measurement\, processing and security solutions for the full stack of telecoms covering device hardware\, radio access and core network protocols. Doug has been involved in device security since 2016 as a co-author of a paper on power side channel analysis that is now the reference in the EMB3D™ framework. He currently works on market development activities for device security in Europe \nIn this session we will discuss the vision and roadmap of applying AI/ML to chip design and verification from what exists today to the “science fiction” future of Generative AI agents working together and orchestrated to design\, verify and debug designs under the guidance of human engineers to further drive innovation beyond what we can imagine today. \nAdvanced RISC-V Virtualizer/Hypervisor Verification for CPU & SoC\nDavid Kelf\, Breker Verification Systems \nThe advent of RISC-V has presented verification teams with many new challenges. As we move towards more system-level verification and RISC-V Application Processors in general\, these types of scenarios will become commonplace. This presentation will discuss a specific complex\, but yet commonplace\, verification challenge for any team working on a complex RISC-V core\, demonstrating the types of scenarios included in the Breker RISC-V SystemVIPs. We will consider the verification of a Memory Management Unit (MMU) that includes virtualization and hypervisor operation. These scenarios need to consider both Single- and Multi-core devices along with an Input Output Memory Management Unit (IOMMU) and uncore IP interaction. The presentation will contain valuable information for any engineer or manager involved with the design of a RISC-V core or using a RISC-V core on their SoC. It will also demonstrate techniques for the verification of complex system scenarios in general. \nBiography \nDave Kelf\, is the CEO of Breker Verification Systems\, the leader in test suite synthesis and SystemVIPs. Previously\, Dave served as vice president of worldwide marketing solutions at formal verification provider OneSpin Solutions. Earlier\, Kelf was president and CEO of Sigmatix\, Inc. He worked in sales and marketing at Cadence Design Systems and was responsible for the Verilog and VHDL verification product lines. As vice president of marketing at Co-Design Automation and then Synopsys\, Kelf oversaw the successful introduction and growth of the SystemVerilog language\, before running marketing for Novas Software\, noted for the Verdi product line\, which became Springsoft and is now part of Synopsys. Dave holds a Bachelor of Science degree in Electronic Computer Systems from the University of Salford and a Master of Science degree in Microelectronics from Brunel University\, both in the U.K.\, and an MBA from Boston University
URL:https://desn.org.uk/event/verification-futures-2025/
CATEGORIES:DESN Partnered Event
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DTSTART;TZID=Europe/London:20250717T163000
DTEND;TZID=Europe/London:20250717T190000
DTSTAMP:20250624T130321Z
CREATED:20250624T130105Z
LAST-MODIFIED:20250624T130321Z
UID:22924-1752769800-1752778800@desn.org.uk
SUMMARY:Innovating for Investment: Harnessing Innovation and IP to Drive Growth
DESCRIPTION:
URL:https://eip.com/uk/latest/events/innovating-for-investment-how-the-right-approach-to-innovation-and-ip-can-help-grow-and-secure-investment#new_tab
LOCATION:Bradford\, CB4 0GA
CATEGORIES:DESN Promoted Event
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