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DTSTART;VALUE=DATE:20250521
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UID:22838-1747785600-1747871999@desn.org.uk
SUMMARY:FPGA Front Runners: Prototyping systems using FPGA
DESCRIPTION:Prototyping systems using FPGARegisterSponsored by Sundance\nWe’ve seen in today’s rapidly evolving industry\, FPGA prototyping plays a crucial role in ASIC design validation and early hardware/software integration. \nThe event will provide invaluable insights into how FPGA-based prototyping can de-risk development\, optimize performance\, and accelerate time-to-market. \nPotential Topics of Interest: \n\nEnsuring Confidence in ASIC Design Before Tapeout – Identifying and resolving potential design flaws before committing to silicon\nEarly Hardware/Software Integration – Bridging the gap between design and implementation to streamline development\nOvercoming Simulation Bottlenecks – Enabling longer\, more complex test scenarios that traditional simulations cannot handle\nAutomotive-Specific FPGA Applications – Exploring how FPGA prototyping is transforming the future of automotive electronics.\n\nWho Should Attend? \n\nASIC Designers – Validate and optimize your designs efficiently.\nAutomotive Engineers – See how FPGA enhances real-world automotive applications.\nEmbedded & System Architects – Leverage FPGA for early integration and debugging.\nTech Leaders & Decision-Makers – Stay ahead of industry trends and network with experts.\n\nAgenda \n\n\n\n\n\n09:00\nArrival and Registration\n\n\n09:30\nSundance – Multi FPGA solution for prototyping\n\n\n09:40\nChipflow -Fast FPGA prototyping with python for Automotive & Industrial\n\n\n10:00\nExostiv Labs- You can’t fix what you don’t see – A plea for visibility in FPGA\n\n\n10:30\nCadence- Use of Prototyping and Emulation in the semiconductor industry in 2025\n\n\n11:00\ndSpace- Enabling detailed HiL testing for electric drives with high speed FPGA\n\n\n11:30\nBreak\n\n\n12:00\nSiemens – How Veloce pro FPGA CS accelerates HW and SW verification closure ?\n\n\n12:30\nWeeteq-Utilising FGPAs to develop real time system response correction\n\n\n13:00\nEtas- The Importance of Deterministic Recompute when Developing ADAS Systems\n\n\n13:30\nSynopsys- EP-Ready Hardware-Assisted-Verification Platforms\n\n\n14:00\nLunch and Factory Tour\n\n\n\n\nSpeakers\nFrederic Leens\nCEO and founder\, Exostiv Labs \nFrederic is the CEO and founder of Exostiv Labs. Before establishing Exostiv Labs\, he worked as a designer and provider of design services for companies such as Barco\, NXP\, Philips\, Atos\, and ASML. This experience spanned various industries using semiconductors\, including finance\, medical imaging\, video and broadcast\, military\, and avionics. With over 20 years of expertise\, Frederic and his co-founders envisioned Exostiv Labs with the belief that properly instrumented FPGAs are crucial for enhancing product quality and streamlining design cycles. \nPresentation: You can’t fix what you don’t see – A plea for visibility in FPGAs \nAs FPGAs become more complex\, the design process has evolved in comprehensiveness. Interestingly\, tools—and sometimes engineers—have become highly specialised for specific tasks\, except for ‘debugging’\, which remains a somewhat vague concept that occurs throughout the entire design cycle. \nIn this brief talk\, we will examine the limitations of traditional methodologies and demonstrate that achieving orders of magnitude greater visibility is crucial for effective FPGA design and debugging. \nMichael O’Sullivan\nEngineering Group Director\, Cadence \nMichael O’Sullivan is an engineering director at Cadence with a focus on verification and is based in Edinburgh\, Scotland. . Michael has been with Cadence for over 27 years with various roles in sales\, marketing and design services. Prior to Cadence he was a design engineer at S3 Group in Dublin\, Ireland and at Philips in Eindhoven\, The Netherlands. Michael has an Masters of Engineering Science from the National University of Ireland. \nPresentation: Use of Prototyping and Emulation in the semiconductor industry in 2025 \nRob Taylor\nCEO\, Chipflow \nRob Taylor is driven by his passion for empowering individuals to unleash their creativity\, believing this will enable new products and business models that we can’t yet imagine. With over 20 years of commercialising open source software\, and two previous successful exits (Rev 10m)\, he combined startup leadership experience with deep technical knowledge to bring the vision\, strategy and delivery. \nPresentation: Fast FPGA prototyping with python for Automotive & Industrial  \nDr Philip Clarke\ndSPACE \nDr Clarke works for dSPACE\, a provider of solutions for the development and test of embedded control systems. He will talk about how FPGA technology supports high fidelity real time tests for complex controllers. \nPresentation: Enabling detailed HiL testing for electric drives with high speed FPGA models  \nFlemming Christensen\nSundance \nFlemming founded Sundance in 1989\, designing and building Multiprocessor solution based around INMOS’s Transputer. \n36 years later and not a lot has changed. \nSundance Multiprocessor Technology Ltd. was founded in 1989 and has thousands of man-years of experience operating as an Original Equipment Manufacturer (OEM). It offers a range of Commercial-of-the-shelf (COTS) boards for a broad range of customers. \nThey have in-house manufacturing equipment for electronics board and full test facilities. We run an ISO9001 Quality System to monitor all processes and have done since 1999. \nPresentation: Multi FPGA solution for prototyping  \nTaner Dosluoglu\nWeeteq \nDr Taner Dosluoglu\, Founder & CEO\nWeeteq \nSemiconductor Executive with decades of successful technology innovation and disruptive product introduction experience \nExperienced Semiconductor Executive with demonstrated history of successful technology innovation and disruptive product introduction in a Start-up environment as well as R&D teams within larger companies. Extensive experience in operations and product development as well as direct technical contributions in analog architecture\, circuits and system level design\, device and process innovations\, and publications in photonics\, semiconductor devices and circuits. \n• Previously: Sarnoff Corporation\, Tektronix\, SRI International\, Dialog Semiconductor\, Chaoyang Technologies\, Endura Technologies.\n• Ph.D. degree in Electrical Engineering in 1992 from Oregon Graduate Institute at Oregon Health Sciences University in Portland\, Oregon. \nJames Dickie\nEtas \nAn experienced product manager with detailed knowledge of emdedded software and development tools in the automotive and general embedded systems markets. \nGraham Harris & Amr EiDieb\nSiemens \nPresentation :How Veloce proFPGA CS accelerates HW and SW verification closure ? \nLearn how Veloce CS Systems are transforming the hardware assisted verification methodology to cope with the market transformation. Part of Veloce CS systems is the comprehensive prototype solution proFPGA CS aimed at maximizing the verification speed\, while offering a configurable capacity scalability from single FPGA to multi-blades/multi-FPGA’s configurations. \nXavier Mathes\nSynopsys \nXavier Mathes is a Principal Application Engineer at Synopsys. He is in charge of the Synopsys HAV products including HAPS\, EP and Synplify for Southern Europe and UK. Xavier previously worked at IBM\, Philips Semiconductor\, Synplicity\, and other semiconductor companies. His combined 28 years working in the industry has brought a wealth of knowledge and experience in the areas of semiconductor design and verification.\nXavier has a Master of Science in Electrical Engineer from CentraleSupelec. \nPresentation: EP-Ready Hardware-Assisted-Verification Platforms \n• Synopsys’ EP2 platforms for supporting emulation and prototyping are advanced solutions designed to accelerate the development and validation of complex semiconductor designs. These platforms provide a unified environment for hardware emulation and FPGA-based prototyping\, enabling engineers to efficiently verify functionality\, debug designs\, and validate system performance. EP2 platforms are highly scalable\, supporting designs ranging from small IP blocks to full-system SoCs. This scalability ensures flexibility for projects of varying complexity. The EP2 platforms utilize high-capacity FPGAs to create accurate prototypes of the design. \n• Prototyping allows enbles for real-world testing and validation\, including performance benchmarking\, power analysis\, and interoperability testing with external systems. \n• These platforms support high-speed interfaces and connectivity for seamless integration with external hardware and software environments. \n• The platforms support early software bring-up and validation\, allowing software teams to test drivers\, firmware\, and applications on the hardware prototype. \n• This reduces the risk of software-hardware integration issues and accelerates time-to-market.
URL:https://desn.org.uk/event/fpga-front-runners-prototyping-systems-using-fpga/
LOCATION:Rolls-Royce Control Systems\, 5000 Solihull Parkway\, Birmingham\, B37 7YH
CATEGORIES:DESN Event
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