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SUMMARY:Trends in Semiconductor System Design
DESCRIPTION:Trends in Semiconductor System Design\nRegister for FREEThank you to our Sponsors\nThe Trends in System Design event\, hosted by DESN in Reading on February 6th\, will be open to both members and non-members. We will examine emerging trends in semiconductor system design\, with a particular focus on how AI/ML is being used in product design and the design flow. \nThe event will also address the challenges in designing IP to meet the compute intensive demands of AI\, including bandwidth and latency issues related to data access\, SoC design challenges\, and obstacles related to the latest technology nodes. \nAdditional topics will cover manufacturing\, testing\, yield challenges\, and the transition to chiplets. \nParticipants will also discuss the process of validating and signing off chips for production\, as well as cost and return-on-investment considerations.\nA second major focus will be on how to best leverage AI’s potential in design flows. Key discussions will explore where AI can be deployed for maximum benefit without introducing risks such as “hallucinations” or security vulnerabilities. \nPresentations will include insights from EDA companies on the features they are incorporating into their tools\, as well as contributions from users who are developing their own solutions. \n\n\n\n\n\nTime\nEvent\n\n\n\n\n09:00\nRegistration\, arrival and refreshments\n\n\n09:25\nIntroduction\n\n\n09:30\nKeynote: Chiplet Standards: A New Route to Arm-based Custom Silicon – Rob Dimond\, System Architect and Fellow\, Arm\n\n\n10:00\nThe Turkey Voting For Christmas – AI and the Verification Engineer – Andrew Bond\, Director – Silicon Verification\, Axelera AI\n\n\n10:30\nImec research: driving advancements in semiconductor technology – Bruno Jansen\, Regional Managing Director\, imec Cambridge UK\n\n\n11:00\nFrom Chips to Systems: Redefining Semiconductor Packaging and Integration – Dr. Jayakrishnan Chandrappan\, CSA Catapult\n\n\n11:30\nBreak\n\n\n12:00\nUsing Generative AI to Transform Chip to Data Center Design Flows – Rod Metcalfe\, Senior Product Management Group Director\, Cadence\n\n\n12:30\nAI-Enabling a Revolution in Chip Design Productivity – Loay Qteet\, Staff Application Engineer\, Synopsys\n\n\n13:00\nUnlocking the AI Advantage with Siemens EDA Products – Sathishkumar Balasubramanian\, Siemens\n\n\n13:30\nTechWorks AI Group  – Dr Mike Bartley\, Senior VP\, Tessolve\n\n\n13:45\nLunch followed by Close\n\n\n\n\nSpeakers\nSathishkumar Balasubramanian\, Senior Director of Product Management\, Marketing & Biz Dev\, Siemens \nUnlocking the AI Advantage with Siemens EDA Products \nWhat’s behind the excitement in the industry around AI? AI is impacting virtually every aspect of semiconductor design. Verifiably accurate AI solutions that “just work” deliver results that users can trust and accelerate schedules\, while reducing the overall resources needed for chip design and verification. At Siemens EDA\, we have successfully leveraged AI technologies to accelerate design and verification.  In this session\, we will provide an overview of state-of-the-art AI-powered solutions encompassing the entire Siemens EDA product portfolio. \nBiography \nSathish currently leads the product management and marketing organization for Solido Custom IC division and AI initiatives at Siemens. Sathish is an experienced product leader with over 20+ years of experience in EDA industry. Sathish’s focus is on bringing value to semiconductor ecosystem through innovative solutions. Sathish is proficient in scaling product portfolio growth and expansion of market share/revenue through relentless focus on data-based execution and thought leadership. \nPrior to Siemens\, Sathish held various product management\, strategic business development and corporate development roles for Cadence Design Systems and Synopsys. Sathish received his BS in Electronics & Communication from University of Madras\, MS in computer engineering from University of Alabama & MBA from UC Berkeley- Hass School of Business. \n\nAndrew Bond\, Director – Silicon Verification\, Axelera AI \nThe Turkey Voting For Christmas – AI and the Verification Engineer \nAs EDA embraces the new opportunities AI brings how will it change what we think of as verification.\nFrom tooling to coding\, from developing to debugging\, from team dynamics to hiring how might things be about to change\, and how can we be best prepared. \nBiography \nAndy has 25 years’ experience as a verification engineer and leader. After starting his career verifying processors for ST he was part of the foundation team for Icera before leading their verification team after the acquisition by NVIDIA.\nHaving since built and developed teams for Cirrus Logic and in fintech\, he is currently director of verification for Axelera AI\, helping solve the verification challenges of the next generation of AI chips. \n\nRob Dimond\, System Architect and Fellow\, Arm \nChiplet Standards: A New Route to Arm-based Custom Silicon \nA key challenge our partners are consistently looking to solve is: How can we continue to push performance boundaries\, with maximum efficiency\, while managing costs associated with manufacturing and yield? Today\, as the ever more complex AI-accelerated computing landscape evolves\, a key solution emerging is chiplets. \nChiplets are designed to be combined to create larger and more complex systems that can be packaged and sold as a single solution\, made of a number of smaller dice instead of one single larger monolithic die. This creates interesting new design possibilities\, with one of the most exciting being a potential route to custom silicon for manufacturers who historically chose off-the-shelf solutions. \nThis talk will describe the standards framework that Arm is building with our partners\, and the broader industry. Including our own specifications such as the Arm Chiplet System Architecture (Arm CSA)\, AMBA chip-to-chip and the role of industry standards such as UCIe. \nBiography \nRob Dimond is System Architect and Fellow at Arm. \nRob is a member of the leadership team for the Architecture and Technology group at Arm where his focus is future technology development for the infrastructure segment (servers & networking). \nPrior to Arm\, Rob was Chief Hardware Architect at FPGA computing start-up Maxeler. Rob holds degrees in Electronic Engineering and Computer Science from Imperial College\, London. \n\nRod Metcalfe\, Senior Product Management Group Director\, Cadence \nUsing Generative AI to Transform Chip to Data Center Design Flows \nDuring this session\, we will delve into advancements in Generative AI technology and its transformative impact on chip design technologies and methodologies. Hear how Generative AI is reshaping chip design\, optimizing chip performance\, and unlocking new possibilities for data center architecture. We will share current case studies\, and future trends that showcase the potential of Generative AI to drive innovation and efficiency in chip design workflows. \nBiography \nRod Metcalfe is a Senior Group Director in the Digital and Signoff product management team at Cadence\, responsible for digital implementation flows and artificial intelligence technology development. He has been involved with EDA for over 20 years\, gaining experience in all parts of the digital design flow from synthesis to sign-off. Before joining EDA\, Rod was a chip designer in the aerospace industry. \n\nDr. Jayakrishnan Chandrappan\, Head of Advanced Packaging\, CSA Catapult \nFrom Chips to Systems: Redefining Semiconductor Packaging and Integration \nThis talk explores the evolution of semiconductor packaging from traditional chip-level approaches to advanced system-level integration. It highlights cutting-edge trends such as 3D integration\, hybrid and heterogeneous integration\, and additive manufacturing\, which are transforming performance\, miniaturization\, and functionality. The session also addresses challenges like thermal management\, sustainability\, and supply chain resilience\, while emphasizing the role of co-design and digital twins in optimising system designs. Attendees will gain insights into how innovative packaging techniques are redefining the semiconductor industry’s capabilities and driving next-generation applications in AI\, IoT\, and beyond. \nBiography \nDr. Jayakrishnan Chandrappan\, Head of Advanced Packaging at CSA Catapult\, has over 25 years of global experience in the semiconductor industry. At CSA Catapult\, he spearheaded the establishment of a state-of-the-art compound semiconductor packaging facility and an expert team driving cutting-edge solutions in semiconductor integration for transformative applications\, including NetZero\, Future Telecoms\, and advanced sensing technologies. \nHe serves as an external advisory board member for the University of Bristol and the University of Leeds in the UK\, and as a Board of Studies member for Cochin University of Science & Technology (CUSAT) in India. His influence is further amplified through his active participation in industry bodies such as SEMI\, the Europe APC Committee\, and the International Microelectronics Assembly & Packaging Society (IMAPS) UK Chapter. \nPreviously\, Dr. Jay held technology leadership roles at Global Foundries Inc. (US)\, IME at A-STAR Singapore\, and as a Scientist for India’s Ministry of Electronics & Information Technology. A co-founder of two start-ups\, his accomplishments include Europe’s most prestigious Marie Skłodowska-Curie Fellowship and the Royal Society of Chemistry’s Emerging Technology Showcase Award.\nHe holds a PhD in materials engineering from University of LEEDS. \n\nBruno Jansen\, Regional Managing Director\, imec Cambridge UK \nImec research: driving advancements in semiconductor technology \nImec is the world’s leading non-profit semiconductor research centre\, dedicated to accelerating semiconductor innovation through collaboration. By pushing Moore’s Law to its limits\, imec continues to scale down the dimensions of logic devices while exploring new pathways at the system level. For decades\, imec has been at the forefront of innovation on the technology side of the ecosystem\, delivering differentiation that has benefited the entire semiconductor industry. To sustain its role in shaping the future of technology\, imec is broadening its focus to address system-scaling challenges in its roadmap. This presentation will provide insights into the research efforts imec is undertaking to further advance semiconductor technology. \nBiography \nBruno Jansen recently joined imec as Regional Managing Director of imec UK and Site Manager of imec Cambridge UK\, focusing on growing the imec Cambridge UK team and exploring collaboration opportunities across the UK. Bruno began his career at Motorola in Toulouse\, working on the design of 3G chipsets. In 2002\, he joined Arm in Cambridge\, initially as a CPU Design Verification Engineer\, and later managed the design verification activities for a CPU product line. He also oversaw operations for UK\, EU\, and US government-funded research programs at Arm Research before becoming Director of Operations for Enterprise Marketing at Arm in 2017. In 2022\, Bruno joined the startup Krai as Director of Operations\, where he was responsible for finance\, recruitment\, and legal compliance. \n\nLoay Qteet\, Staff Application Engineer\, Synopsys \nAI-Enabling a Revolution in Chip Design Productivity \nIn the rapidly evolving semiconductor industry\, an unprecedented productivity challenge is being confronted\, driven by a global talent shortage and increasing demands to accelerate chip design development while managing complexity and cost. This session will delve into the role of Artificial Intelligence as a transformative solution\, highlighting its potential to enable new levels of efficiency in the chip design process. \nBiography \nLoay Qteet\, Applications Engineering\, Staff Engineer at Synopsys\, with six years of experience in the Electronic Design Automation (EDA) field. He specializes in physical design\, RTLIIGDS flow development\, and EDA applications of Implementation and AI. Loay has played a key role in supporting various customer\, helping them to achieve their goals effectively and ensuring that Synopsys products meet their evolving requirements. \n\nDr Mike Bartley\, Senior VP\, Tessolve  \nTechWorks AI Group \nDr Mike Bartley has over 35 years of experience in software testing and hardware verification. He has built and managed state-of-the-art test and verification teams inside several companies (including STMicroelectronics\, Infineon\, Panasonic\, and the start-up ClearSpeed) and also advised several companies on organisational verification strategies (ARM\, NXP\, and multiple start-ups). He has been working on the application of artificial intelligence (AI) since using genetic algorithms in 1998 and now helps companies to adopt best practice AI in DV to improve the productivity and quality of their verification. \nMike successfully founded and grew a software test and hardware verification services company to 450+ engineers globally\, delivering services and solutions to over 50+ clients in various technologies and industries. The company was acquired by Tessolve Semiconductors where he is now Senior VP driving sales in Europe\, global DV strategies\, and R&D into adoption of AI and best practice. Tessolve is a a global company with 3000+ employees supporting clients in VLSI\, silicon test and qualification\, PCB\, and embedded product development in multiple vertical industries.
URL:https://desn.org.uk/event/trends-in-semiconductor-system-design/
LOCATION:Novotel Reading Centre\, 25b Friar Street\, Reading\, RG1 1DP
CATEGORIES:TechWorks Event
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DTSTART;TZID=Europe/London:20250218T090000
DTEND;TZID=Europe/London:20250218T140000
DTSTAMP:20250124T191208Z
CREATED:20241220T183504Z
LAST-MODIFIED:20250124T191208Z
UID:19608-1739869200-1739887200@desn.org.uk
SUMMARY:FPGA FRONT RUNNER : Using AI in development and product for FPGA
DESCRIPTION:FPGA FRONT RUNNER : Using AI in development and product for FPGARegisterThe FPGA Front Runner event aims to bring together FPGA design and verification communities to discuss gate array-related topics. Participants can share knowledge\, learn about current developments\, and network with others. \nThe FPGA Front Runner event\, themed “Using AI in development and product for FPGA\,” is scheduled for Tuesday\, 18th February 2025\, from 9:00 AM to 2:00 PM at Renishaw\, UK. For more information and registration\, visit https://www.tickettailor.com/events/alpinumconsulting/1505991 \nA few speaker slots are still open for industry experts to share their insights. If you’re interested in presenting\, please contact Mike Bartley at mike.bartley@tessolve.com. \nAgenda (GMT) \n \n\n\n\n\nTime\nSpeaker\nDetails\n\n\n\n\n09.00\nArrival and registration\n\n\n\n09.30\nPete Leonard\, Renishaw\nIntroduction to Renishaw\n\n\n09.40\nGareth Richards\, AI Manager\, TechWorks\nTechWorks\n\n\n10.00\nAlexander Montgomerie Corcoran\, CEO\, Heronic\nHeronic\n\n\n10:30\nDavid Harold\, Chief Operating Officer\, RED Semiconductor\nRED Semiconductor\n\n\n11.00\nPedro Machado\, Senior Lecturer in Computer Science\, Nottingham Trent University\nNottingham Trent\n\n\n11:30\nRefreshment break\n\n\n\n12:00\nJeremy Bennett\, Embecosm\n\n\n\n12:30\nTBC\n\n\n\n13:00\nTBC\n\n\n\n13::30\nLunch\n\n\n\n14:00\nClose\n\n\n\n\n\n\nPrior to the main event\, we are pleased to offer a pre-event overview showcasing the key areas of discussion on Tuesday\, 21st Jan 2025. We kindly request your attendance for a 30-minute preview.
URL:https://desn.org.uk/event/fpga-front-runner-using-ai-in-development-and-product-for-fpga/
LOCATION:Renishaw\, Wotton-Under-Edge\, GL12 8JR\, United Kingdom
CATEGORIES:DESN Event
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