BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//DESN - ECPv6.17.1//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-WR-CALNAME:DESN
X-ORIGINAL-URL:https://desn.org.uk
X-WR-CALDESC:Events for DESN
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:Europe/London
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20210328T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20211031T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20220327T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20221030T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20230326T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20231029T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20220210T180000
DTEND;TZID=Europe/London:20220210T190000
DTSTAMP:20220408T091929Z
CREATED:20220121T134734Z
LAST-MODIFIED:20220408T091929Z
UID:18107-1644516000-1644519600@desn.org.uk
SUMMARY:Synopsys: 3DIC Design from Concept to Silicon
DESCRIPTION:Synopsys: 3DIC Design from Concept to Silicon\nREGISTERFor some high-performance computing (HPC) designs\, monolithic SoCs aren’t producing the scalability and yield that designers are looking for. New trends towards 3DIC design are emerging introducing new design challenges\, such as reliable die-to-die connectivity\, high bandwidth memory\, integration\, and 2.5D or 3D packaging options. This webinar will outline the different market trends for 3DIC designs and explain how designers can maintain such new trends to deliver their designs with optimized latency\, power\, performance\, and area. We will also demonstrate the construction of a 3DIC design and our 3rd generation HBM interposer auto-routing solution. \nAttendees will: \n\nLearn about considerations and trends for a more efficient 3DIC design integration\nFind out how protocols like HBM3 and Die-to-Die are influencing 3DIC designs\nSee a demo of a 3DIC design construction\n\nSPEAKERS\nKenneth Larsen is a product marketing director in the Silicon Realization Group at Synopsys. He is a versatile leader with a strong background in defining and executing product vision\, marketing strategy\, inspiring product development teams\, translating technology concepts into customer solutions\, developing high-performance global organizations\, conceiving and driving new and emerging products to scale from the ground up\, guiding marketing\, and enabling sales. Kenneth has a degree in electrical engineering and additional coursework in strategic growth at Columbia Business School\, and Artificial Intelligence at MIT Sloan School of Management. \nEric Means is an Applications Engineer in Hillsboro\, Oregon supporting Synopsys 3DIC Compiler users. He has worked with ASIC and EDA customers for 25 years at NEC\, Renesas\, & Synopsys. He has a BS in Electrical Engineering from Washington State University and an MS in Computer Engineering from the Oregon Graduate Institute. \n*This webinar is in partnership with SemiWiki and Synopsys*
URL:https://desn.org.uk/event/synopsys-3dic-design-from-concept-to-silicon/
CATEGORIES:Past Event,Promoted Event
ATTACH;FMTTYPE=image/jpeg:https://desn.org.uk/wp-content/uploads/2022/01/3DIC-Design-from-Concept-to-Silicon-Max-Quality.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20220209T173000
DTEND;TZID=Europe/London:20220209T180000
DTSTAMP:20220728T130826Z
CREATED:20220121T135503Z
LAST-MODIFIED:20220728T130826Z
UID:18110-1644427800-1644429600@desn.org.uk
SUMMARY:Synopsys: Exploring a Software First Approach to Avoid SoC Re-spins
DESCRIPTION:Synopsys: Exploring a Software First Approach to Avoid SoC Re-spins\nREGISTERTraditional coverage-based verification methods are no longer sufficient to verify complex SoCs integrating many processor cores and IP subsystems.  To conquer the verification challenge of complex SoCs\, companies are shifting their development paradigm to a software first approach.  By considering the target software up front\, as a critical part of the SoC development process\, designs teams are able to signoff a new SoC for production with high confidence. \nIn this Synopsys webinar we will cover the primary pre-silicon methods\, along with their benefits\, to execute a software first strategy: \n– Virtual prototyping\n– Emulation\n– FPGA-based prototyping \nThrough the example of a production processor design project\, we will provide insight into each methodology and how it helps to accelerate verification coverage.  This event is hosted by a software first methodology expert and aimed at verification and software teams working on next-generation SoC designs.
URL:https://desn.org.uk/event/synopsys-exploring-a-software-first-approach-to-avoid-soc-re-spins/
CATEGORIES:Past Event
ATTACH;FMTTYPE=image/png:https://desn.org.uk/wp-content/uploads/2022/02/synweb2.png
END:VEVENT
END:VCALENDAR