BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//DESN - ECPv6.17.1//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-WR-CALNAME:DESN
X-ORIGINAL-URL:https://desn.org.uk
X-WR-CALDESC:Events for DESN
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:UTC
BEGIN:STANDARD
TZOFFSETFROM:+0000
TZOFFSETTO:+0000
TZNAME:UTC
DTSTART:20210101T000000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Europe/London
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20210328T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20211031T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20220327T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20221030T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20230326T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20231029T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;VALUE=DATE:20220309
DTEND;VALUE=DATE:20220310
DTSTAMP:20220728T125841Z
CREATED:20220218T133517Z
LAST-MODIFIED:20220728T125841Z
UID:18335-1646784000-1646870399@desn.org.uk
SUMMARY:Synopsys: Early and Accelerated SoC Connectivity Verification using VC Formal Connectivity Checking App
DESCRIPTION:Synopsys: Early and Accelerated SoC Connectivity Verification using VC Formal Connectivity Checking App\nRegisterComplex bus protocols\, increased on-chip functionalities\, coupled with limited shared I/O resources\, result in complex wiring connections in SoCs with numerous muxing schemes.\nSimulation and structural analysis approaches require huge effort and may lead to bug escapes making them inefficient for SoC connectivity verification. Connectivity verification using formal techniques is exhaustive and helps making designs immune to connectivity bug escapes. \nFor over a decade\, VC Formal Connectivity Checking App has become an essential part of the verification toolkit used by leading edge technology companies. Its ability to scale with the ever increasing SoC design sizes\, its performance and ease of use\, and its optimized debugging capabilities\, make it a market leader in this space. \nJoin us to learn about SoC connectivity challenges and how Synopsys’ innovative technologies can help you catch and debug sneaky wiring mistakes early with 100% confidence and ease.
URL:https://desn.org.uk/event/synopsys-early-and-accelerated-soc-connectivity-verification-using-vc-formal-connectivity-checking-app/
CATEGORIES:Past Event,Promoted Event
ATTACH;FMTTYPE=image/png:https://desn.org.uk/wp-content/uploads/2022/02/synweb2.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20220303T120000
DTEND;TZID=Europe/London:20220303T123000
DTSTAMP:20220408T091436Z
CREATED:20220207T153850Z
LAST-MODIFIED:20220408T091436Z
UID:18174-1646308800-1646310600@desn.org.uk
SUMMARY:Rules of Origin when exporting to the EU
DESCRIPTION:RULES OF ORIGIN WHEN EXPORTING TO THE EU\nRegister for FREEWhere your product comes from or is made\, can have a huge impact on the tariffs applicable when selling to another country. Ensuring your goods comply with the rules of origin in the EU/UK Trade & Cooperation Agreement is essential for you to export your product smoothly and avoid costly errors.\nAs of 1st January 2022\, to benefit from the reduced rate of Customs Duty\, all companies exporting goods to the EU must be able to prove that their goods are of UK/EU origin – it is no longer sufficient to make a declaration on your commercial invoice. Inability to do so may result in delays\, demands for duty and even penalties. \nThis essential one-hour webinar led by TechWorks and The International Trade Consultancy will cover: \n\nWhat are rules of origin?\nWhich rules of origin apply to my products?\nHow can I check if they comply?\nHow can I prove they comply?\nWhat should I do if they don’t comply?\nWhat is cumulation and does it apply to me?\n\nHosted by\nLucinda O’Reilly \nLucinda O’Reilly is an international trade consultant with over 10 years’ experience of global imports and exports. As the Exports Director of Ecotile Flooring she developed a successful UK focused manufacturing company to export to over 40 countries worldwide. Having successfully managed Ecotile’s transition through Brexit Lucinda set up The International Trade Consultancy to provide support to companies struggling to navigate the new regulatory landscape and supply chain challenges caused by the pandemic.
URL:https://desn.org.uk/event/rules-of-origin-when-exporting-to-the-eu/
CATEGORIES:NMI Event,Past Event
ATTACH;FMTTYPE=image/jpeg:https://desn.org.uk/wp-content/uploads/2022/02/webinarv2.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20220223T080000
DTEND;TZID=UTC:20220406T170000
DTSTAMP:20220728T131600Z
CREATED:20220217T192307Z
LAST-MODIFIED:20220728T131600Z
UID:18334-1645603200-1649264400@desn.org.uk
SUMMARY:Cadence TECHTALK Series: Adopting a Faster\, More Efficient Path to Multi-Chiplet Design
DESCRIPTION:Cadence TECHTALK Series: Adopting a Faster\, More Efficient Path to Multi-Chiplet Design\nRegisterWith the increasing popularity of multi-chiplet designs that address Moore’s law slowdown and reticle size limitations\, leading foundries are offering multiple advanced packaging and die stacking options for different applications.\nEDA companies have had to innovate to provide integrated and IC-centric tools while building accurate system-level models to find the fastest and most efficient path for 3D-IC design and analysis. \nIn this four-part CadenceTECHTALK series\, learn how to properly plan and implement stacked digital SoCs\, analog/mixed-signal designs\, and entire 2.5-D/3-D systems\, including meeting system-level power and thermal analysis requirements through an integrated 3D-IC solution.
URL:https://desn.org.uk/event/cadence-techtalk-series-adopting-a-faster-more-efficient-path-to-multi-chiplet-design/
CATEGORIES:Past Event
ATTACH;FMTTYPE=image/jpeg:https://desn.org.uk/wp-content/uploads/2022/02/cad3.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20220217T120000
DTEND;TZID=Europe/London:20220217T123000
DTSTAMP:20220408T092109Z
CREATED:20220207T154453Z
LAST-MODIFIED:20220408T092109Z
UID:18164-1645099200-1645101000@desn.org.uk
SUMMARY:Commodity Codes and Import Declarations
DESCRIPTION:COMMODITY CODES AND IMPORT DECLARATIONS\nRegister for FREEOn January 1st 2022\, two changes came into effect that importers and exporters should be aware of. The World Customs Organisation updated the Harmonised System so there have been a number of changes to commodity codes\, especially for electronic products.\nFull import declarations are now required for all goods entering GB from the EU at point of import and a new digital system is in place to manage the increase in data. \nThis essential 30 minute webinar led by TechWorks and The International Trade Consultancy will cover: \n\nWhat are commodity codes?\nHow can I check my commodity codes are still correct?\nWhat do I need to do if they’ve changed?\nHow does the new import declaration system work?\nHow will it affect my business?\n\nHosted by\nLucinda O’Reilly \nLucinda O’Reilly is an international trade consultant with over 10 years’ experience of global imports and exports. As the Exports Director of Ecotile Flooring she developed a successful UK focused manufacturing company to export to over 40 countries worldwide. Having successfully managed Ecotile’s transition through Brexit Lucinda set up The International Trade Consultancy to provide support to companies struggling to navigate the new regulatory landscape and supply chain challenges caused by the pandemic.
URL:https://desn.org.uk/event/commodity-codes-and-import-declarations/
CATEGORIES:NMI Event,Past Event
ATTACH;FMTTYPE=image/jpeg:https://desn.org.uk/wp-content/uploads/2022/02/webinarsv1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20220210T180000
DTEND;TZID=Europe/London:20220210T190000
DTSTAMP:20220408T091929Z
CREATED:20220121T134734Z
LAST-MODIFIED:20220408T091929Z
UID:18107-1644516000-1644519600@desn.org.uk
SUMMARY:Synopsys: 3DIC Design from Concept to Silicon
DESCRIPTION:Synopsys: 3DIC Design from Concept to Silicon\nREGISTERFor some high-performance computing (HPC) designs\, monolithic SoCs aren’t producing the scalability and yield that designers are looking for. New trends towards 3DIC design are emerging introducing new design challenges\, such as reliable die-to-die connectivity\, high bandwidth memory\, integration\, and 2.5D or 3D packaging options. This webinar will outline the different market trends for 3DIC designs and explain how designers can maintain such new trends to deliver their designs with optimized latency\, power\, performance\, and area. We will also demonstrate the construction of a 3DIC design and our 3rd generation HBM interposer auto-routing solution. \nAttendees will: \n\nLearn about considerations and trends for a more efficient 3DIC design integration\nFind out how protocols like HBM3 and Die-to-Die are influencing 3DIC designs\nSee a demo of a 3DIC design construction\n\nSPEAKERS\nKenneth Larsen is a product marketing director in the Silicon Realization Group at Synopsys. He is a versatile leader with a strong background in defining and executing product vision\, marketing strategy\, inspiring product development teams\, translating technology concepts into customer solutions\, developing high-performance global organizations\, conceiving and driving new and emerging products to scale from the ground up\, guiding marketing\, and enabling sales. Kenneth has a degree in electrical engineering and additional coursework in strategic growth at Columbia Business School\, and Artificial Intelligence at MIT Sloan School of Management. \nEric Means is an Applications Engineer in Hillsboro\, Oregon supporting Synopsys 3DIC Compiler users. He has worked with ASIC and EDA customers for 25 years at NEC\, Renesas\, & Synopsys. He has a BS in Electrical Engineering from Washington State University and an MS in Computer Engineering from the Oregon Graduate Institute. \n*This webinar is in partnership with SemiWiki and Synopsys*
URL:https://desn.org.uk/event/synopsys-3dic-design-from-concept-to-silicon/
CATEGORIES:Past Event,Promoted Event
ATTACH;FMTTYPE=image/jpeg:https://desn.org.uk/wp-content/uploads/2022/01/3DIC-Design-from-Concept-to-Silicon-Max-Quality.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20220209T173000
DTEND;TZID=Europe/London:20220209T180000
DTSTAMP:20220728T130826Z
CREATED:20220121T135503Z
LAST-MODIFIED:20220728T130826Z
UID:18110-1644427800-1644429600@desn.org.uk
SUMMARY:Synopsys: Exploring a Software First Approach to Avoid SoC Re-spins
DESCRIPTION:Synopsys: Exploring a Software First Approach to Avoid SoC Re-spins\nREGISTERTraditional coverage-based verification methods are no longer sufficient to verify complex SoCs integrating many processor cores and IP subsystems.  To conquer the verification challenge of complex SoCs\, companies are shifting their development paradigm to a software first approach.  By considering the target software up front\, as a critical part of the SoC development process\, designs teams are able to signoff a new SoC for production with high confidence. \nIn this Synopsys webinar we will cover the primary pre-silicon methods\, along with their benefits\, to execute a software first strategy: \n– Virtual prototyping\n– Emulation\n– FPGA-based prototyping \nThrough the example of a production processor design project\, we will provide insight into each methodology and how it helps to accelerate verification coverage.  This event is hosted by a software first methodology expert and aimed at verification and software teams working on next-generation SoC designs.
URL:https://desn.org.uk/event/synopsys-exploring-a-software-first-approach-to-avoid-soc-re-spins/
CATEGORIES:Past Event
ATTACH;FMTTYPE=image/png:https://desn.org.uk/wp-content/uploads/2022/02/synweb2.png
END:VEVENT
END:VCALENDAR