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DTSTART;TZID=Europe/London:20260416T100000
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DTSTAMP:20260413T174628Z
CREATED:20260116T151918Z
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SUMMARY:FPGA Frontrunners Event
DESCRIPTION:FPGA Frontrunner EventREGISTERCLICK HERE to find out more about the FPGA FrontrunnersField Programmable Gate Arrays (FPGAs) play a critical role in modern electronic systems\, powering applications that range from everyday consumer products to mission-critical infrastructure. Their ability to be customized and reconfigured after deployment makes them uniquely valuable in fast-moving technology environments. At the same time\, this adaptability introduces distinct security challenges that must be carefully addressed. \nBecause FPGAs can be reprogrammed in the field\, they present a broader attack surface than fixed-function hardware. Threats targeting configuration data\, intellectual property\, firmware integrity\, and runtime behavior can compromise not only the device itself\, but also the larger systems that rely on it. As FPGAs are increasingly used to support advanced workloads—including data-intensive and intelligent processing—security risks continue to grow in both scope and impact. \nEffective FPGA security extends beyond physical protection. It encompasses the full lifecycle and ecosystem surrounding the device\, including design tools\, bitstreams\, firmware\, software interfaces\, and data flows. In systems that incorporate adaptive or AI-assisted functionality\, ensuring trust\, integrity\, and resilience across this ecosystem is especially critical. \nThis event explores the evolving landscape of FPGA security\, highlighting emerging threats\, recent advances\, and proven mitigation strategies. Through expert insights and real-world case studies\, the program aims to equip engineers\, researchers\, and security professionals with practical guidance for securing FPGA-based systems today and in \nknowledge\, techniques\, and assurance frameworks necessary to design systems that are not only resilient and secure—but demonstrably so. \nWho Should Attend\nFPGA Designers and EngineersSystem ArchitectsSafety and Security SpecialistsSupply Chain ProfessionalsIndustry Regulators and Standards Bodies \nWhy Attend? \n\nGain insights from leading experts on the evolving risks and mitigation strategies\nLearn how to meet functional safety and security requirements across multiple industries\nNetwork with industry peers and potential collaborators\nParticipate in discussions on best practices\, regulatory trends\, and real-world case studies\n\nOutline Agenda\n\n\n\n\nTime\nDetails\n\n\n\n\n10:00\nRegistration\n\n\n10:30\nMicrochip Secure FPGA’sIan PearsonPr. ESE\, Microchip\n\n\n11:00\nA Visual Demonstration of True Random Numbers from a Quantum ComputerPhill J PaynePrincipal Digital Design Engineer\, Novomorphic\n\n\n11:30\nAre FPGAs unique for security?Martin ThompsonSenior Technical Specialist\, ZF Engineering Solutions\n\n\n12:00\nBeyond Bitstream Encryption: FPGA Security for High-Assurance SystemsDaniel TeeSenior Firmware (FPGA) Engineer\, Leonardo\n\n\n12:30\nNetworking Lunch\n\n\n13:30\nOverview of prEN50767 : CRA Vertical Standard for FPGA/ASICPeter TrottStaff FAE\, Microchip\n\n\n14:00\nHardware-Rooted Bitstream SecurityMans AhmadianChief Innovation Officer\, Sundance\n\n\n14:30\nWrap Up\n\n\n14:45\nClose\n\n\n\n\nPhill J Payne\, Principal Digital Design Engineer\, Novomorphic\nPresentation: A Visual Demonstration of True Random Numbers from a Quantum Computer \nTrue randomness is one of those things everyone assumes they have… right up until security\, trust\, or assurance actually matters.\nThis session reveals a practical way to pull physical entropy from a real quantum computer and inject it into FPGA and embedded systems as a usable\, engineering-grade input. You’ll see quantum behaviour turned into something tangible and immediate — a live “quantum dice” demonstrator that makes the invisible visible — and you’ll learn why this matters far beyond novelty. \nWe’ll explore what changes when your randomness isn’t “noisy enough” pseudo-random\, but rooted in genuine physical uncertainty\, and how that can reshape thinking around key generation\, nonces\, reseeding\, and trusted system design. A live comparison between simulation and real quantum hardware draws a clear line between “looks random” and “is random”. \nIf you build secure edge systems and care about trust boundaries\, this will change how you think about entropy. \nprofile×Phill J Payne\nPhill J Payne is Principal Digital Design Engineer at Novomorphic\, specialising in secure\, real-time FPGA and embedded architectures for edge AI. He is developing convolution acceleration and a modular hardware fabric that composes reconfigurable pipelines\, reduces memory pressure\, and delivers high-performance vision and inference at the edge. Across 26 years\, Phill has turned novel architectural ideas into deployable systems under tight power\, latency\, throughput\, and reliability constraints\, with deep experience in security-grade FPGA development and signal-processing workloads. Previously\, he delivered end-to-end FPGA firmware and software for advanced systems\, including a patented communications technique designed to operate in contested jamming environments\, later acquired by a major defence prime. He also built specialised training systems used in preparation for the London 2012 Olympic Games\, translating complex engineering into practical tools. \nMartin Thompson\, Senior Technical Specialist\,  ZF Engineering Solutions\nPresentation: Are FPGAs unique for security?\n \nIn this talk we will investigate the degree to which systems containing programmable logic (including FPGAs) can be considered “unique” in their security requirements and implementation options\, when compared to more conventional microcontroller and desktop processor systems. \nWe will briefly define what we mean by “security” in this context (both in terms of market requirements and attacker motivations) and what primitives can be used to achieve it. A review of the variety of potential attacks will be presented and we will spend some time on the peculiarities of FPGA-based systems by comparing them directly with other implementation strategies. Finally\, we will conclude with an answer to the question posed in the title. \nprofile×Martin Thompson\nMartin Thompson is a Senior Technical Specialist at ZF Engineering Solutions. He has spent over 30 years developing systems and algorithms for products in the automotive and aerospace domains. He enjoys working across the full range of software and electronics disciplines\, from desktop algorithm development to microcontroller\, DSP and FPGA code as well as electronic design\, PCB layout (and when the need arises\, soldering!). He specialises in optimisations of whole electronic systems\, based on a detailed understanding of the trade-offs across multiple domains. Particular highlights have included the development of very low-cost FPGA-based imaging and radar-systems. \nSince 2015\, Martin has been heavily involved in the cybersecurity of embedded systems and is currently the technical leader of an penetration-testing team with an embedded-system focus. He contributes to the Internet of Things Security Foundation Assurance Framework\, the Automotive Threat Matrix\, and is a member of the MITRE hardware CWE SIG and the CWE-RTL working group. Finally\, he spends some of his time researching novel side-channel attacks in pursuit of a PhD\, with the University of Durham. \nMans Ahmadian\, Chief Innovation Officer\, Sundance\n\nPresentation: Hardware-Rooted Bitstream Security and Secure Manufacturing Workflow\n \nA Defense-Grade Implementation Using PolarFire FPGA on Sundance PCIe104N Platform As FPGAs become central to mission-critical defense and aerospace systems\, the security challenge has shifted. It is no longer enough to protect configuration data in the fi eld; we must also secure it during manufacturing\, programming\, testing\, and across the entire supply chain. When production is distributed across multiple facilities and third-party partners\, the FPGA bitstream becomes a high-value target\, vulnerable to interception\, overbuilding\, hardware substitution\, or reverse engineering. This talk presents a defence-grade secure provisioning workflow implemented on the Sundance PCIe104N platform\, built around the PolarFire MPF500T FPGA\, and explains how it establishes trust from silicon to system deployment. \nRead More \nAt the heart of this approach is hardware-rooted security. PolarFire devices generate a unique\, silicon-derived identity using Physically Unclonable Functions (PUFs)\, meaning that no two FPGAs are electrically identical and no identity can be copied or cloned. During secure provisioning\, this identity is validated before any sensitive key material is transferred. The customer’s encrypted bitstream and User Encryption Key are generated inside their own trusted environment and securely delivered for programming using Microchip’s Secure Production Programming Solution. If authentication fails at any stage\, such as in a dummy FPGA impersonation attempt\, the process stops immediately. No keys are exposed\, and no firmware is released. What this workflow ultimately provides is confidence. Confidence that the hardware being programmed is genuine. Confidence that only the approved number of boards can ever be provisioned. Confidence that the bitstream cannot be intercepted\, modified\, or extracted through side-channel attacks. By combining controlled manufacturing\, independent validation\, hardware security modules\, authenticated encryption\, and built-in DPA countermeasures\, Sundance ensures customers receive fully tested\, securely programmed boards\, without any risk of supply-chain compromise or intellectual property leakage. Today\, I will walk you through how this architecture works and why it sets a scalable model for secure FPGA manufacturing. \n\nprofile×Mans Ahmadian\nMans Ahmadian serves as the Chief Innovation Officer at Sundance\, where he leads the architecture of next-generation\, high-density AI Systems-on-Modules (SoMs). In this role\, he directs the design of specialized AI Engines and systems otimized for low-power\, high-throughput inference in rugged environments. He is instrumental in bridging the gap between AI frameworks and SundanceDSP hardware. Additionally\, his work ensures the reliability of autonomous Edge AI platforms in mission-critical settings by optimizing SWaP (Size\, Weight\, and Power) solutions and integrating safety-critical\, “fail-safe” R&D workflows. \nThroughout his career\, he has been granted numerous patents for his innovations in image processing\, advanced camera systems and imaging sensor operations. His technical and commercial achievements have earned him several prestigious honors\, including the IET (Institute of Engineering and Technology) Innovation Award in software development\, the SMART::SCOTLAND Innovation Award\, and a Business Plan Competition win. These accolades are supported by a robust academic foundation\, including a PhD in Medical Image Processing\, an MSc in Biomedical/Medical Engineering\, and a BSc in Electronics from The University of Edinburgh\, and postgraduate certificates in Health Data Science and Big Data and AI. \nDaniel Tee\, Senior Firmware (FPGA) Engineer\, Leonardo\n\nPresentation: Beyond Bitstream Encryption: FPGA Security for High-Assurance Systems\n \nField programmable gate arrays (FPGAs) are increasingly deployed in systems where failure or compromise is not an option – from defence and aerospace to critical infrastructure and advanced industrial platforms. In these high assurance environments\, security requirements extend beyond the protections normally offered by device vendors. Engineers must consider the broader context of threats\, deployment conditions\, and system level risk. \nRead More \nThis presentation explores the evolving landscape of FPGA security and outlines practical considerations for designing and deploying secure programmable logic systems. It introduces the principles that shape high assurance engineering\, highlights common security challenges unique to reconfigurable hardware\, and discusses methods for establishing trust from initial configuration through runtime operation. The talk also touches on modern approaches to isolation\, secure execution\, and configuration protection\, alongside emerging trends that FPGA developers should be aware of as threats and technologies continue to advance. \nAttendees will gain a clearer understanding of how to think about security in FPGA based systems\, along with a set of concepts and design patterns that can be adapted to a wide range of high assurance applications. \n\nprofile×Daniel Tee\nDaniel Tee is a Senior Firmware (FPGA) Engineer at Leonardo\, working within the product security team. He joined Leonardo as a graduate in 2022 after completing an integrated MEng in Electronics and Computer Science at the University of Edinburgh\, where he focused on a number of cybersecurity modules in his final year. Daniel now applies his interest in hardware security to developing robust FPGA‑based security solutions for customer‑driven\, mission‑critical applications. \nIan Pearson\, Pr. ESE\, Microchip Technology Inc.\n\nPresentation: Leveraging Microchip Secure FPGAs\n \nThe foundation of a secure end product lies in the right choice of components. CRA requires a ‘Secure by Design’ approach to product development and support throughout the lifecycle. Microchip FPGA’s have a long history of secure FPGA’s designed to meet the most demanding of military applications but available to all \nprofile×Ian Pearson\nIan Pearson is a Principle Embedded Solutions Engineer with Microchip Technology covering FPGA\, Security and IoT. He is also the chair of the IoT Security Foundation – Security Assurance Framework Working Group. \nPeter Trott\, Staff FAE\, Microchip Technology Inc.\n\nPresentation: Overview of prEN50767 : CRA Vertical Standard for FPGA/ASIC\n \nThe EU CRA requirements can be met via a presumption of conformity using horizontal and vertical harmonised standards. These standards are in development and will release very close to the enforcement date. In this session we will give some insight into what is coming in the vertical standard for FPGA/ASIC. The prEN50767 standard provides the requirements for FPGA/ASIC vendors to meet the Important Class I categorisation of FPGA/ASIC in the EU CRA. \nprofile×Peter Trott\nPeter Trott is a Staff Applications engineer at Microchip with over 30yrs experience in the FPGA sector. He has extensive experience in both military and industrial design using FPGA’s. Peter is also a key member of the EU TC47x WG4 Trusted Silicon work group for FPGA/ASIC who are creating the prEN50767 harmonised standard relative to the Important Class I FPGA/ASIC with security features
URL:https://desn.org.uk/event/fpga-frontrunner-2026/
LOCATION:Microchip\, 720 Wharfedale Road\, Winnersh\, RG41 5TP
CATEGORIES:DESN Event
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BEGIN:VEVENT
DTSTART;VALUE=DATE:20260614
DTEND;VALUE=DATE:20260618
DTSTAMP:20260428T171041Z
CREATED:20260428T170947Z
LAST-MODIFIED:20260428T171041Z
UID:23586-1781395200-1781740799@desn.org.uk
SUMMARY:29th World Micromachining Summit
DESCRIPTION:
URL:https://mms2026.soton.ac.uk/#new_tab
LOCATION:Southampton
CATEGORIES:DESN Promoted Event
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DTSTART;TZID=Europe/London:20260617T091500
DTEND;TZID=Europe/London:20260617T172000
DTSTAMP:20260428T171515Z
CREATED:20260224T120629Z
LAST-MODIFIED:20260428T171515Z
UID:23346-1781687700-1781716800@desn.org.uk
SUMMARY:Women in TechWorks: Engineering Intelligently
DESCRIPTION:Women in TechWorks Launch EventRegisterConnecting Talent\nWomen in TechWorks comes together in person for the first time — bringing the community to the heart of the UK’s technology ecosystem. \nHosted at Arm\, this landmark event builds on the program created through tech talks\, town halls and fireside chats. \nWhy Attend?\nTechWorks sits at the centre of the UK’s leading technology communities — semiconductors\, embedded systems\, cybersecurity\, future compute and AI. \nOn 17 June\, we bring together the full spectrum of talent across these sectors for a day of: \n\nInspiring talks from exceptional women in industry\nPanel discussions spanning leadership\, innovation and visibility\nNetworking across career stages — from early careers to founders and C-suite leaders\n\nWho It’s For\nThis event is open to everyone. \nWhile it showcases outstanding women shaping UK technology\, it’s designed for everyone \, and be part of a stronger\, more inclusive tech ecosystem. \nFrom Momentum to Action\nWomen in TechWorks is focused on: \n\nLeadership\nMentorship\nVisibility\n\nThis first face-to-face event brings those pillars to life \nJoin us for a day that connects people\, ideas and opportunity.
URL:https://techworks.org.uk/event/women-in-techworks-engineering-intelligently/#new_tab
LOCATION:Arm\, Cambridge\, CB1 9NJ
CATEGORIES:TechWorks Event
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DTSTART;VALUE=DATE:20260623
DTEND;VALUE=DATE:20260624
DTSTAMP:20260511T083050Z
CREATED:20260414T123406Z
LAST-MODIFIED:20260511T083050Z
UID:23540-1782172800-1782259199@desn.org.uk
SUMMARY:Verification & Semiconductors Futures Conference UK 2026
DESCRIPTION:Verification Futures UK 2026\, co-located with Semiconductors Futures 2026 co-organised by Tessolve and Alpinum.\nThe conference continues its strong tradition of delivering a unique blend of conference presentations\, exhibitions\, training\, and industry networking sessions focused on the challenges faced in hardware and software verification. The event remains an important forum for end-users to define their verification challenges and collaborate with engineers\, researchers\, and vendors to shape practical solutions. In 2026\, Verification Futures continues to strengthen its core emphasis on verification methodologies\, DV tools\, and engineering workflows\, including areas such as formal methods for complex SoCs\, CPU & RISC-V verification\, open-source and licence-free verification tools\, AI in design verification (AI in DV)\, verification planning and coverage\, and HW/SW co-verification. \nSemiconductors Futures 2026 brings together the semiconductor community\, covering AI/ML in IP & SoC design\, AI’s impact on EDA and workflows\, FPGA & mixed-signal\, with a focus on the automotive\, data centre\, and AI products. New tracks consider emerging technologies such as quantum computing\, photonics\, and chiplets\, as well as startups and investments. We expect 50+ engineering students to attend a separate session. \nDetailsSimon Southwell\nSystems Consultant\nWyvern Semiconductors \n×Simon Southwell\nComplex protocol modelling with OSVVM co-simulation\, exploring the PCIe VC \nA look at OSVVM co-simulation features and their use for constructing complex protocol verification component using PCIe as an example. It looks at the integration of the PCIe GEN1/GEN2 C model from the presenter’s pcieVHost project\, using OSVVM’s co-simulation capabilities\, to construct an OSVVM compatible Verification Component (VC)\, used like any other VHDL based VC\, but with additional features\, to drive 3rd party PCIe IP. An example of driving Altera’s Cyclone V Hard IP for PCI Express is discussed. \nBiography \nEngineer with 35+ years in R&D\, with experience in ASIC design\, FPGA\, and embedded software development. Currently working on developing open-source IP in areas such as co-simulation and system modelling. A collaborator on the OSVVM project\, adding and supporting its co-simulation capabilities and developing verification IP. \nAreas of experiences include logic IP for both ASIC and FPGA\, logic verification\, HPC\, processor systems\, networking (802.3 and proprietary)\, embedded software\, co-simulation technology\, software modelling of SoC systems\, data compression logic\, PCIe endpoint design\, cellular (3G and 4G)\, wireless (802.11 and 802.15.4). Joint or sole author on several logic IP related patents. \nDetailsRojalin Mishra\nLead Verification Engineer\nRiver Lane \n×Rojalin Mishra\nFrom Qubits to Confidence: Verifying Quantum Error Correction \nQuantum error correction (QEC) introduces fundamentally new challenges for verification\, where probabilistic behaviour and correlated errors break many conventional methodologies. This talk explores how we adapt verification strategies to this domain\, including designing testbenches for probabilistic measurement data\, modelling spatially and temporally correlated noise\, and defining meaningful coverage for error correction circuits. \nThrough real debugging case studies\, we highlight subtle failure modes unique to quantum systems—such as silent corruption during syndrome extraction—and discuss approaches to validating decoder behaviour across complex syndrome spaces. We also examine how verification can be performed under realistic noise distributions to build confidence in system-level reliability. \nBio: I am an Electronics and Communications engineer with over a decade of experience in ASIC/FPGA verification\, specialising in complex digital systems and verification methodologies. I currently serve as a Lead Verification Engineer\, driving UVM-based verification for Quantum Error Correction within the rapidly evolving field of Quantum Computing. \nDetailsSteinn Gustafsson\nFounder\nChevin Technology \n×Steinn Gustafsson\nPresentation Title: Complex protocol modelling with OSVVM co-simulation\, exploring the PCIe VC \nA look at OSVVM co-simulation features and their use for constructing complex protocol verification component using PCIe as an example. It looks at the integration of the PCIe GEN1/GEN2 C model from the presenter’s pcieVHost project\, using OSVVM’s co-simulation capabilities\, to construct an OSVVM compatible Verification Component (VC)\, used like any other VHDL based VC\, but with additional features\, to drive 3rd party PCIe IP. An example of driving Altera’s Cyclone V Hard IP for PCI Express is discussed. \nBio: Engineer with 35+ years in R&D\, with experience in ASIC design\, FPGA\, and embedded software development. Currently working on developing open-source IP in areas such as co-simulation and system modelling. A collaborator on the OSVVM project\, adding and supporting its co-simulation capabilities and developing verification IP. \nAreas of experiences include logic IP for both ASIC and FPGA\, logic verification\, HPC\, processor systems\, networking (802.3 and proprietary)\, embedded software\, co-simulation technology\, software modelling of SoC systems\, data compression logic\, PCIe endpoint design\, cellular (3G and 4G)\, wireless (802.11 and 802.15.4). Joint or sole author on several logic IP related patents. \nDetailsYassine Eben Aimine\nSiemens \n×Yassine Eben Aimine\nYassine has more than 20 years’ experience in the EDA industry. Throughout his professional career\, Yassine has partnered with design and verification engineers to deploy the latest technologies in EDA tooling in the areas of design for test\, functional verification\, and functional safety. \nDetailsPhill J Payne\nPrincipal Digital Design Engineer\nNovomorphic \n×Phill J Payne\nPhill J Payne is Principal Digital Design Engineer at Novomorphic\, specialising in secure\, real-time FPGA and embedded architectures for edge AI. He is developing convolution acceleration and a modular hardware fabric that composes reconfigurable pipelines\, reduces memory pressure\, and delivers high-performance vision and inference at the edge. Across 26 years\, Phill has turned novel architectural ideas into deployable systems under tight power\, latency\, throughput\, and reliability constraints\, with deep experience in security-grade FPGA development and signal-processing workloads. Previously\, he delivered end-to-end FPGA firmware and software for advanced systems\, including a patented communications technique designed to operate in contested jamming environments\, later acquired by a major defence prime. He also built specialised training systems used in preparation for the London 2012 Olympic Games\, translating complex engineering into practical tools. \nDetailsGavin Lofts\nField Applications Engineer\nAltera \n×Gavin Lofts\nGavin Lofts is a Field Applications Engineer at Altera with 20+ years of experience in hardware\, embedded software\, and FPGA design. He has worked on systems ranging from biosensors to radio. \nPresentation: CI/CD and Git for Modern FPGA Development
URL:https://desn.org.uk/event/verification-semiconductors-futures-conference-uk-2026/
LOCATION:University of Reading\, Whiteknights PO Box 217\, Reading\, Berkshire\, RG6 6AH\, United Kingdom
CATEGORIES:DESN Event,DESN Promoted Event
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DTSTART;TZID=Europe/London:20260820T140000
DTEND;TZID=Europe/London:20260820T150000
DTSTAMP:20260511T121055Z
CREATED:20260511T121055Z
LAST-MODIFIED:20260511T121055Z
UID:23636-1787234400-1787238000@desn.org.uk
SUMMARY:Women in TechWorks: From Qubits to Confidence: Verifying Quantum Error Correction
DESCRIPTION:
URL:https://us06web.zoom.us/webinar/register/WN_jqtxyiffRPmeJwEHwqzaVA#new_tab
LOCATION:Webinar
CATEGORIES:TechWorks Event
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BEGIN:VEVENT
DTSTART;VALUE=DATE:20260826
DTEND;VALUE=DATE:20260827
DTSTAMP:20260422T090649Z
CREATED:20260422T090649Z
LAST-MODIFIED:20260422T090649Z
UID:23562-1787702400-1787788799@desn.org.uk
SUMMARY:TechWorks Semiconductors to Systems Summit 2026
DESCRIPTION:
URL:https://techworks.org.uk/techworks/tws2s26/#new_tab
CATEGORIES:DESN Event,TechWorks Event
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