FPGA Frontrunner Event: FPGA Safety and Security
2024-11-21 09:30 - 14:00 (Europe/London) | The Cass Centre, Cambridge, CB2 8BS
FPGA Safety and Security
Agenda (GMT)

Time
Speaker
Details

09.30
Arrival and registration

10.00
Tobias Adryan, Synopsys
Securing FPGAs Beyond the Bitstream

10.30
Espen Tallaksen, EmLogic
FPGA Requirements Tracking and the Requirements Traceability Matrix

11.00
Andrew Swirski, Beetlebox
Securing FPGA Development Pipelines with DevSecOps

11.30
Refreshment break

12.00
Ian Pearson, Microchip Technology Inc.
EU Cyber Resilience Act – Impacts on Business and Product Design

12.30
Flemming Christensen, Sundance Multiprocessor Technology Ltd
How to secure supply of ‘COTS’ FPGA Modules

13.00
Speaker TBD

13.30
Lunch and networking

14.00
End

NOTE
Please be aware that if you register for both the in-person and virtual events, your physical ticket will be cancelled, preventing access on the event day.
We also maintain a blacklist; individuals who register for the in-person event but fail to attend will be restricted from participating in future events. If you book a physical ticket but cannot attend then please cancel it in advance.

Location
The Cass Centre, Shaftesbury Road, Cambridge, CB2 8BS

Select tickets

Need help?
Manage tickets

Trends in Semiconductor System Design
2025-02-06 08:30 - 17:00 | Novotel Reading Centre, 25b Friar Street, Reading, RG1 1DP
Trends in Semiconductor System Design
Register for FREEThank you to our Sponsors
The Trends in System Design event, hosted by DESN in Reading on February 6th, will be open to both members and non-members. We will examine emerging trends in semiconductor system design, with a particular focus on how AI/ML is being used in product design and the design flow.
The event will also address the challenges in designing IP to meet the compute intensive demands of AI, including bandwidth and latency issues related to data access, SoC design challenges, and obstacles related to the latest technology nodes.
Additional topics will cover manufacturing, testing, yield challenges, and the transition to chiplets.
Participants will also discuss the process of validating and signing off chips for production, as well as cost and return-on-investment considerations.
A second major focus will be on how to best leverage AI’s potential in design flows. Key discussions will explore where AI can be deployed for maximum benefit without introducing risks such as “hallucinations” or security vulnerabilities.
Presentations will include insights from EDA companies on the features they are incorporating into their tools, as well as contributions from users who are developing their own solutions.

Time
Event

09:00
Registration, arrival and refreshments

09:25
Introduction

09:30
Keynote: Chiplet Standards: A New Route to Arm-based Custom Silicon – Rob Dimond, System Architect and Fellow, Arm

10:00
The Turkey Voting For Christmas – AI and the Verification Engineer – Andrew Bond, Director – Silicon Verification, Axelera AI

10:30
Imec research: driving advancements in semiconductor technology – Bruno Jansen, Regional Managing Director, imec Cambridge UK

11:00
From Chips to Systems: Redefining Semiconductor Packaging and Integration – Dr. Jayakrishnan Chandrappan, CSA Catapult

11:30
Break

12:00
Using Generative AI to Transform Chip to Data Center Design Flows – Rod Metcalfe, Senior Product Management Group Director, Cadence

12:30
AI-Enabling a Revolution in Chip Design Productivity – Loay Qteet, Staff Application Engineer, Synopsys

13:00
Unlocking the AI Advantage with Siemens EDA Products – Sathishkumar Balasubramanian, Siemens

13:30
TechWorks AI Group – Dr Mike Bartley, Senior VP, Tessolve

13:45
Lunch followed by Close

Speakers
Sathishkumar Balasubramanian, Senior Director of Product Management, Marketing & Biz Dev, Siemens
Unlocking the AI Advantage with Siemens EDA Products
What’s behind the excitement in the industry around AI? AI is impacting virtually every aspect of semiconductor design. Verifiably accurate AI solutions that “just work” deliver results that users can trust and accelerate schedules, while reducing the overall resources needed for chip design and verification. At Siemens EDA, we have successfully leveraged AI technologies to accelerate design and verification. In this session, we will provide an overview of state-of-the-art AI-powered solutions encompassing the entire Siemens EDA product portfolio.
Biography
Sathish currently leads the product management and marketing organization for Solido Custom IC division and AI initiatives at Siemens. Sathish is an experienced product leader with over 20+ years of experience in EDA industry. Sathish’s focus is on bringing value to semiconductor ecosystem through innovative solutions. Sathish is proficient in scaling product portfolio growth and expansion of market share/revenue through relentless focus on data-based execution and thought leadership.
Prior to Siemens, Sathish held various product management, strategic business development and corporate development roles for Cadence Design Systems and Synopsys. Sathish received his BS in Electronics & Communication from University of Madras, MS in computer engineering from University of Alabama & MBA from UC Berkeley- Hass School of Business.

Andrew Bond, Director – Silicon Verification, Axelera AI
The Turkey Voting For Christmas – AI and the Verification Engineer
As EDA embraces the new opportunities AI brings how will it change what we think of as verification.
From tooling to coding, from developing to debugging, from team dynamics to hiring how might things be about to change, and how can we be best prepared.
Biography
Andy has 25 years’ experience as a verification engineer and leader. After starting his career verifying processors for ST he was part of the foundation team for Icera before leading their verification team after the acquisition by NVIDIA.
Having since built and developed teams for Cirrus Logic and in fintech, he is currently director of verification for Axelera AI, helping solve the verification challenges of the next generation of AI chips.

Rob Dimond, System Architect and Fellow, Arm
Chiplet Standards: A New Route to Arm-based Custom Silicon
A key challenge our partners are consistently looking to solve is: How can we continue to push performance boundaries, with maximum efficiency, while managing costs associated with manufacturing and yield? Today, as the ever more complex AI-accelerated computing landscape evolves, a key solution emerging is chiplets.
Chiplets are designed to be combined to create larger and more complex systems that can be packaged and sold as a single solution, made of a number of smaller dice instead of one single larger monolithic die. This creates interesting new design possibilities, with one of the most exciting being a potential route to custom silicon for manufacturers who historically chose off-the-shelf solutions.
This talk will describe the standards framework that Arm is building with our partners, and the broader industry. Including our own specifications such as the Arm Chiplet System Architecture (Arm CSA), AMBA chip-to-chip and the role of industry standards such as UCIe.
Biography
Rob Dimond is System Architect and Fellow at Arm.
Rob is a member of the leadership team for the Architecture and Technology group at Arm where his focus is future technology development for the infrastructure segment (servers & networking).
Prior to Arm, Rob was Chief Hardware Architect at FPGA computing start-up Maxeler. Rob holds degrees in Electronic Engineering and Computer Science from Imperial College, London.

Rod Metcalfe, Senior Product Management Group Director, Cadence
Using Generative AI to Transform Chip to Data Center Design Flows
During this session, we will delve into advancements in Generative AI technology and its transformative impact on chip design technologies and methodologies. Hear how Generative AI is reshaping chip design, optimizing chip performance, and unlocking new possibilities for data center architecture. We will share current case studies, and future trends that showcase the potential of Generative AI to drive innovation and efficiency in chip design workflows.
Biography
Rod Metcalfe is a Senior Group Director in the Digital and Signoff product management team at Cadence, responsible for digital implementation flows and artificial intelligence technology development. He has been involved with EDA for over 20 years, gaining experience in all parts of the digital design flow from synthesis to sign-off. Before joining EDA, Rod was a chip designer in the aerospace industry.

Dr. Jayakrishnan Chandrappan, Head of Advanced Packaging, CSA Catapult
From Chips to Systems: Redefining Semiconductor Packaging and Integration
This talk explores the evolution of semiconductor packaging from traditional chip-level approaches to advanced system-level integration. It highlights cutting-edge trends such as 3D integration, hybrid and heterogeneous integration, and additive manufacturing, which are transforming performance, miniaturization, and functionality. The session also addresses challenges like thermal management, sustainability, and supply chain resilience, while emphasizing the role of co-design and digital twins in optimising system designs. Attendees will gain insights into how innovative packaging techniques are redefining the semiconductor industry’s capabilities and driving next-generation applications in AI, IoT, and beyond.
Biography
Dr. Jayakrishnan Chandrappan, Head of Advanced Packaging at CSA Catapult, has over 25 years of global experience in the semiconductor industry. At CSA Catapult, he spearheaded the establishment of a state-of-the-art compound semiconductor packaging facility and an expert team driving cutting-edge solutions in semiconductor integration for transformative applications, including NetZero, Future Telecoms, and advanced sensing technologies.
He serves as an external advisory board member for the University of Bristol and the University of Leeds in the UK, and as a Board of Studies member for Cochin University of Science & Technology (CUSAT) in India. His influence is further amplified through his active participation in industry bodies such as SEMI, the Europe APC Committee, and the International Microelectronics Assembly & Packaging Society (IMAPS) UK Chapter.
Previously, Dr. Jay held technology leadership roles at Global Foundries Inc. (US), IME at A-STAR Singapore, and as a Scientist for India’s Ministry of Electronics & Information Technology. A co-founder of two start-ups, his accomplishments include Europe’s most prestigious Marie Skłodowska-Curie Fellowship and the Royal Society of Chemistry’s Emerging Technology Showcase Award.
He holds a PhD in materials engineering from University of LEEDS.

Bruno Jansen, Regional Managing Director, imec Cambridge UK
Imec research: driving advancements in semiconductor technology
Imec is the world’s leading non-profit semiconductor research centre, dedicated to accelerating semiconductor innovation through collaboration. By pushing Moore’s Law to its limits, imec continues to scale down the dimensions of logic devices while exploring new pathways at the system level. For decades, imec has been at the forefront of innovation on the technology side of the ecosystem, delivering differentiation that has benefited the entire semiconductor industry. To sustain its role in shaping the future of technology, imec is broadening its focus to address system-scaling challenges in its roadmap. This presentation will provide insights into the research efforts imec is undertaking to further advance semiconductor technology.
Biography
Bruno Jansen recently joined imec as Regional Managing Director of imec UK and Site Manager of imec Cambridge UK, focusing on growing the imec Cambridge UK team and exploring collaboration opportunities across the UK. Bruno began his career at Motorola in Toulouse, working on the design of 3G chipsets. In 2002, he joined Arm in Cambridge, initially as a CPU Design Verification Engineer, and later managed the design verification activities for a CPU product line. He also oversaw operations for UK, EU, and US government-funded research programs at Arm Research before becoming Director of Operations for Enterprise Marketing at Arm in 2017. In 2022, Bruno joined the startup Krai as Director of Operations, where he was responsible for finance, recruitment, and legal compliance.

Loay Qteet, Staff Application Engineer, Synopsys
AI-Enabling a Revolution in Chip Design Productivity
In the rapidly evolving semiconductor industry, an unprecedented productivity challenge is being confronted, driven by a global talent shortage and increasing demands to accelerate chip design development while managing complexity and cost. This session will delve into the role of Artificial Intelligence as a transformative solution, highlighting its potential to enable new levels of efficiency in the chip design process.
Biography
Loay Qteet, Applications Engineering, Staff Engineer at Synopsys, with six years of experience in the Electronic Design Automation (EDA) field. He specializes in physical design, RTLIIGDS flow development, and EDA applications of Implementation and AI. Loay has played a key role in supporting various customer, helping them to achieve their goals effectively and ensuring that Synopsys products meet their evolving requirements.

Dr Mike Bartley, Senior VP, Tessolve
TechWorks AI Group
Dr Mike Bartley has over 35 years of experience in software testing and hardware verification. He has built and managed state-of-the-art test and verification teams inside several companies (including STMicroelectronics, Infineon, Panasonic, and the start-up ClearSpeed) and also advised several companies on organisational verification strategies (ARM, NXP, and multiple start-ups). He has been working on the application of artificial intelligence (AI) since using genetic algorithms in 1998 and now helps companies to adopt best practice AI in DV to improve the productivity and quality of their verification.
Mike successfully founded and grew a software test and hardware verification services company to 450+ engineers globally, delivering services and solutions to over 50+ clients in various technologies and industries. The company was acquired by Tessolve Semiconductors where he is now Senior VP driving sales in Europe, global DV strategies, and R&D into adoption of AI and best practice. Tessolve is a a global company with 3000+ employees supporting clients in VLSI, silicon test and qualification, PCB, and embedded product development in multiple vertical industries.

FPGA FRONT RUNNER : Using AI in development and product for FPGA
2025-02-18 09:00 - 14:00 | Renishaw, Wotton-Under-Edge, GL12 8JR, United Kingdom
FPGA FRONT RUNNER : Using AI in development and product for FPGARegisterThe FPGA Front Runner event aims to bring together FPGA design and verification communities to discuss gate array-related topics. Participants can share knowledge, learn about current developments, and network with others.
The FPGA Front Runner event, themed “Using AI in development and product for FPGA,” is scheduled for Tuesday, 18th February 2025, from 9:00 AM to 2:00 PM at Renishaw, UK. For more information and registration, visit https://www.tickettailor.com/events/alpinumconsulting/1505991
A few speaker slots are still open for industry experts to share their insights. If you’re interested in presenting, please contact Mike Bartley at mike.bartley@tessolve.com.
Agenda (GMT)

Time
Speaker
Details

09.00
Arrival and registration

09.30
Pete Leonard, Renishaw
Introduction to Renishaw

09.40
Gareth Richards, AI Manager, TechWorks
TechWorks

10.00
Alexander Montgomerie Corcoran, CEO, Heronic
Heronic

10:30
David Harold, Chief Operating Officer, RED Semiconductor
RED Semiconductor

11.00
Pedro Machado, Senior Lecturer in Computer Science, Nottingham Trent University
Nottingham Trent

11:30
Refreshment break

12:00
Jeremy Bennett, Embecosm

12:30
TBC

13:00
TBC

13::30
Lunch

14:00
Close

Prior to the main event, we are pleased to offer a pre-event overview showcasing the key areas of discussion on Tuesday, 21st Jan 2025. We kindly request your attendance for a 30-minute preview.

FPGA Front Runners: Prototyping systems using FPGA
2025-05-21 | Rolls-Royce Control Systems, 5000 Solihull Parkway, Birmingham, B37 7YH
Prototyping systems using FPGARegisterSponsored by Sundance
We’ve seen in today’s rapidly evolving industry, FPGA prototyping plays a crucial role in ASIC design validation and early hardware/software integration.
The event will provide invaluable insights into how FPGA-based prototyping can de-risk development, optimize performance, and accelerate time-to-market.
Potential Topics of Interest:

Ensuring Confidence in ASIC Design Before Tapeout – Identifying and resolving potential design flaws before committing to silicon
Early Hardware/Software Integration – Bridging the gap between design and implementation to streamline development
Overcoming Simulation Bottlenecks – Enabling longer, more complex test scenarios that traditional simulations cannot handle
Automotive-Specific FPGA Applications – Exploring how FPGA prototyping is transforming the future of automotive electronics.

Who Should Attend?

ASIC Designers – Validate and optimize your designs efficiently.
Automotive Engineers – See how FPGA enhances real-world automotive applications.
Embedded & System Architects – Leverage FPGA for early integration and debugging.
Tech Leaders & Decision-Makers – Stay ahead of industry trends and network with experts.

Agenda

09:00
Arrival and Registration

09:30
Sundance – Multi FPGA solution for prototyping

09:40
Chipflow -Fast FPGA prototyping with python for Automotive & Industrial

10:00
Exostiv Labs- You can’t fix what you don’t see – A plea for visibility in FPGA

10:30
Cadence- Use of Prototyping and Emulation in the semiconductor industry in 2025

11:00
dSpace- Enabling detailed HiL testing for electric drives with high speed FPGA

11:30
Break

12:00
Siemens – How Veloce pro FPGA CS accelerates HW and SW verification closure ?

12:30
Weeteq-Utilising FGPAs to develop real time system response correction

13:00
Etas- The Importance of Deterministic Recompute when Developing ADAS Systems

13:30
Synopsys- EP-Ready Hardware-Assisted-Verification Platforms

14:00
Lunch and Factory Tour

Speakers
Frederic Leens
CEO and founder, Exostiv Labs
Frederic is the CEO and founder of Exostiv Labs. Before establishing Exostiv Labs, he worked as a designer and provider of design services for companies such as Barco, NXP, Philips, Atos, and ASML. This experience spanned various industries using semiconductors, including finance, medical imaging, video and broadcast, military, and avionics. With over 20 years of expertise, Frederic and his co-founders envisioned Exostiv Labs with the belief that properly instrumented FPGAs are crucial for enhancing product quality and streamlining design cycles.
Presentation: You can’t fix what you don’t see – A plea for visibility in FPGAs
As FPGAs become more complex, the design process has evolved in comprehensiveness. Interestingly, tools—and sometimes engineers—have become highly specialised for specific tasks, except for ‘debugging’, which remains a somewhat vague concept that occurs throughout the entire design cycle.
In this brief talk, we will examine the limitations of traditional methodologies and demonstrate that achieving orders of magnitude greater visibility is crucial for effective FPGA design and debugging.
Michael O’Sullivan
Engineering Group Director, Cadence
Michael O’Sullivan is an engineering director at Cadence with a focus on verification and is based in Edinburgh, Scotland. . Michael has been with Cadence for over 27 years with various roles in sales, marketing and design services. Prior to Cadence he was a design engineer at S3 Group in Dublin, Ireland and at Philips in Eindhoven, The Netherlands. Michael has an Masters of Engineering Science from the National University of Ireland.
Presentation: Use of Prototyping and Emulation in the semiconductor industry in 2025
Rob Taylor
CEO, Chipflow
Rob Taylor is driven by his passion for empowering individuals to unleash their creativity, believing this will enable new products and business models that we can’t yet imagine. With over 20 years of commercialising open source software, and two previous successful exits (Rev 10m), he combined startup leadership experience with deep technical knowledge to bring the vision, strategy and delivery.
Presentation: Fast FPGA prototyping with python for Automotive & Industrial
Dr Philip Clarke
dSPACE
Dr Clarke works for dSPACE, a provider of solutions for the development and test of embedded control systems. He will talk about how FPGA technology supports high fidelity real time tests for complex controllers.
Presentation: Enabling detailed HiL testing for electric drives with high speed FPGA models
Flemming Christensen
Sundance
Flemming founded Sundance in 1989, designing and building Multiprocessor solution based around INMOS’s Transputer.
36 years later and not a lot has changed.
Sundance Multiprocessor Technology Ltd. was founded in 1989 and has thousands of man-years of experience operating as an Original Equipment Manufacturer (OEM). It offers a range of Commercial-of-the-shelf (COTS) boards for a broad range of customers.
They have in-house manufacturing equipment for electronics board and full test facilities. We run an ISO9001 Quality System to monitor all processes and have done since 1999.
Presentation: Multi FPGA solution for prototyping
Taner Dosluoglu
Weeteq
Dr Taner Dosluoglu, Founder & CEO
Weeteq
Semiconductor Executive with decades of successful technology innovation and disruptive product introduction experience
Experienced Semiconductor Executive with demonstrated history of successful technology innovation and disruptive product introduction in a Start-up environment as well as R&D teams within larger companies. Extensive experience in operations and product development as well as direct technical contributions in analog architecture, circuits and system level design, device and process innovations, and publications in photonics, semiconductor devices and circuits.
• Previously: Sarnoff Corporation, Tektronix, SRI International, Dialog Semiconductor, Chaoyang Technologies, Endura Technologies.
• Ph.D. degree in Electrical Engineering in 1992 from Oregon Graduate Institute at Oregon Health Sciences University in Portland, Oregon.
James Dickie
Etas
An experienced product manager with detailed knowledge of emdedded software and development tools in the automotive and general embedded systems markets.
Graham Harris & Amr EiDieb
Siemens
Presentation :How Veloce proFPGA CS accelerates HW and SW verification closure ?
Learn how Veloce CS Systems are transforming the hardware assisted verification methodology to cope with the market transformation. Part of Veloce CS systems is the comprehensive prototype solution proFPGA CS aimed at maximizing the verification speed, while offering a configurable capacity scalability from single FPGA to multi-blades/multi-FPGA’s configurations.
Xavier Mathes
Synopsys
Xavier Mathes is a Principal Application Engineer at Synopsys. He is in charge of the Synopsys HAV products including HAPS, EP and Synplify for Southern Europe and UK. Xavier previously worked at IBM, Philips Semiconductor, Synplicity, and other semiconductor companies. His combined 28 years working in the industry has brought a wealth of knowledge and experience in the areas of semiconductor design and verification.
Xavier has a Master of Science in Electrical Engineer from CentraleSupelec.
Presentation: EP-Ready Hardware-Assisted-Verification Platforms
• Synopsys’ EP2 platforms for supporting emulation and prototyping are advanced solutions designed to accelerate the development and validation of complex semiconductor designs. These platforms provide a unified environment for hardware emulation and FPGA-based prototyping, enabling engineers to efficiently verify functionality, debug designs, and validate system performance. EP2 platforms are highly scalable, supporting designs ranging from small IP blocks to full-system SoCs. This scalability ensures flexibility for projects of varying complexity. The EP2 platforms utilize high-capacity FPGAs to create accurate prototypes of the design.
• Prototyping allows enbles for real-world testing and validation, including performance benchmarking, power analysis, and interoperability testing with external systems.
• These platforms support high-speed interfaces and connectivity for seamless integration with external hardware and software environments.
• The platforms support early software bring-up and validation, allowing software teams to test drivers, firmware, and applications on the hardware prototype.
• This reduces the risk of software-hardware integration issues and accelerates time-to-market.

Verification Futures 2025 - FEATURING tracks from DESN and TechWorks AI
2025-07-01
Verification Futures 2025RegisterJoin us at the verification futures event taking place on 1st July 2025 in Reading.
As part of the expanded agenda for Verification Futures UK 2025, a brand-new Design Track will debut, hosted by the connected networks of Techworks (Techworks AI and DESN). This track will focus on the latest advances in AI-enabled IP, next-generation SoC and semiconductor design, and breakthrough technologies transforming the electronics landscape.
The Verification Futures conference has always provided a unique blend of presentations, exhibitions, and industry networking — offering a platform for end-users to define verification challenges and collaborate with engineers and vendors to create solutions. In 2025, Verification Futures UK is expanding to reflect the evolving landscape of semiconductor design, with a strong focus on AI/ML applications in IP/SoC, FPGA, and Mixed Signal designs.
Attendees will gain access to cutting-edge technical content and expert presentations in
• AI-Enhanced Semiconductor and IP Design
• Next-Generation IP Architectures and Verification Strategies
• Innovative Design Methodologies and Flows
• Emerging and Breakthrough Technologies
• Design for AI/ML Acceleration and Edge Computing<
Why Attend the Design Track?
• Gain technical insights from industry-leading engineers, architects, and researchers
• Learn from cutting-edge research and case studies addressing real-world design and verification challenges
• Network with 250+ onsite professionals and 1,000+ virtual participants across the semiconductor and verification ecosystem
• Engage with emerging talent from the UK Electronics Skills Foundation (UKESF) showcasing their work
• Collaborate with UK’s leading semiconductor startups through SiCatalyst UK
• Be inspired by keynote addresses from visionaries, including Sean Redmond

Design Track Agenda

Time
Name
Talk Title

11:30
Martin Zeller, Dream Chip
Three approaches to cope with rising ASIC complexity

11:50
Gareth Richards, Techworks
TechWorks-AI and TAIBOM – Engineering Trustable AI

12:10
James Lewis, Red Semiconductor
RISC-V: Innovating Within An Established Architecture

Break

13:30
Bradley Geden
The Era of Agentic Engineering – Roadmap to Level 5

14:00
John Wickerson, Imperial College London
Testing and verifying the tools of hardware design

14:20
Doug Carsen

14:40
Speaker TBC

15:00
Speaker TBC

15:20
Cristian Sestito, University of Edinburgh
TrIM: An Efficient Systolic Array for Convolutional Neural Networks

15:40
Speaker TBC

Introducing New Tracks!
Verification Futures 2025 will feature exciting new additions:
• IP Stream: Explore the latest trends and solutions in intellectual property (IP) verification.
• FPGA Track: Explore FPGA verification techniques
• Mixed Signal
• Verification Projects using Open Source/License-Free Tools
Registration
Register now to become a part of this event in-person or online.
Click here to register.
Testing and verifying the tools of hardware design
John Wickerson, Senior Lecturer, Imperial College London
Hardware engineers rely on several tools to build hardware, such as high-level synthesis tools to convert C code into Verilog, logic synthesis tools to convert Verilog into netlists, and so on until they end up with a design that can be implemented on an FPGA or fabricated on an ASIC. Mistakes are difficult and expensive to rectify, so engineers routinely use formal equivalence checkers to double-check that each transformation is correct. All these tools are critical pieces of software infrastructure and are highly trusted… but are they trustworthy? At Imperial, we have been developing new techniques for testing and verifying hardware design tools. We have found bugs in all of the tools we have tested, even the formal equivalence checkers. Some of these bugs cause the tools simply to crash; others are more sinister, causing the tools to produce incorrect results. We are also prototyping new hardware design tools that come with a mechanically checked proof of their own correctness and thus promise the highest standard of reliability. The work is led by my current and former PhD students Yann Herklotz, Quentin Corradi, and Michalis Pardalos, and is also in collaboration with George Constantinides, Alastair Donaldson, Emiliano Morini, and Laura Pozzi.
Biography
John Wickerson is a Senior Lecturer in the Department of Electrical and Electronic Engineering at Imperial College London. His research is at the intersection of programming languages and hardware design
TechWorks-AI and TAIBOM – Engineering Trustable AI
Gareth Richards, Network Manager, TechWorks AI
Outline of the new Techworks-AI community, bringing together members, regardless of sector of operation, who have a common interest in AI/ML technology, developments and applications and an overview of the TAIBOM.
Biography
Gareth has over 35 years’ experience leading the design and development of electronic systems used by millions of people every day in the UK, United States and Japan, including highly secure EAL4+ point of sale products used
Testing and verifying the tools of hardware design
John Wickerson, Imperial College London
Hardware engineers rely on several tools to build hardware, such as high-level synthesis tools to convert C code into Verilog, logic synthesis tools to convert Verilog into netlists, and so on until they end up with a design that can be implemented on an FPGA or fabricated on an ASIC. Mistakes are difficult and expensive to rectify, so engineers routinely use formal equivalence checkers to double-check that each transformation is correct. All these tools are critical pieces of software infrastructure and are highly trusted… but are they trustworthy? At Imperial, we have been developing new techniques for testing and verifying hardware design tools. We have found bugs in all of the tools we have tested, even the formal equivalence checkers. Some of these bugs cause the tools simply to crash; others are more sinister, causing the tools to produce incorrect results. We are also prototyping new hardware design tools that come with a mechanically checked proof of their own correctness and thus promise the highest standard of reliability. The work is led by my current and former PhD students Yann Herklotz, Quentin Corradi, and Michalis Pardalos, and is also in collaboration with George Constantinides, Alastair Donaldson, Emiliano Morini, and Laura Pozzi.
Biography
John Wickerson is a Senior Lecturer in the Department of Electrical and Electronic Engineering at Imperial College London. His research is at the intersection of programming languages and hardware design
Rethinking chip(let) design for next generation ADAS applications
Martin Zeller, Dream Chip
Three approaches to cope with rising ASIC complexity.
Biography
Martin is responsible for the SoC development at Dreamchip, a Tessolve company.
He has a diploma in electrical engineering from Leibniz University of Hannover and a business diploma from the University of Hagen. For more than 25 years he has developed ASICs and architectures, mainly for video coding and imaging; starting with Infineon’s first mobile phone camera, later enhancing Silicon Image’s HDMI interface ASICs to TV processor SoCs. In the last years he mainly worked on latest generation ADAS SoCs for several major players in the automotive industry.
In 2010 Martin joined DreamChip Technologies GmbH as the Head of SoC Design. In 2016 his team designed the world’s first 22nm ADAS SoC based on ARM’s Cortex A53 application processor and ARM’s Cortex R5 lockstep safety core as a platform for further developments. In the last years, several automotive SoCs based on this platform have been built by Dreamchip.
In 2022 and 2023 new generations of Dreamchip’s platform have been taped out.
Martin also worked as a trainer for ARM Cortex processor integration.
The Era of Agentic Engineering – Roadmap to Level 5
Bradley Geden, Synopsys
We are now in the era of pervasive intelligence from voice assistants, advanced robotics, drone-based delivery to autonomous cars, and chatbots. This begs the question, how are we doing in design verification? Design verification is one of the most expensive and time-consuming activities for any chip design. Moreover, every year the cost of design verification grows exponentially and despite that ½ of design re-spins are caused by functional or logic bugs.
With the advent of Large Language Models (LLM) and Generative Pre-Trained Transformer (GPT) models, what are the possibilities in design verification?
In this session we will discuss the vision and roadmap of applying AI/ML to chip design and verification from what exists today to the “science fiction” future of Generative AI agents working together and orchestrated to design, verify and debug designs under the guidance of human engineers to further drive innovation beyond what we can imagine today.
Biography
Bradley Geden is the Senior Director of Product Management for Verification Software at Synopsys based in Sunnyvale, CA. He has over 20 years of experience in the EDA industry covering a broad range of domains from Custom Design, Circuit Simulation, Digital Implementation and Verification in both Product Management and Sales Roles at Synopsys and Siemens EDA. Prior to entering the world of EDA he was an Analog Mixed-Signal Design Engineer working on Energy Measurement and Wireless Communication Chips. In his spare time, Bradley enjoys travelling and exploring the world with his wife, preferably on a sail boat!
In this session we will discuss the vision and roadmap of applying AI/ML to chip design and verification from what exists today to the “science fiction” future of Generative AI agents working together and orchestrated to design, verify and debug designs under the guidance of human engineers to further drive innovation beyond what we can imagine today.
Pre-silicon Identification of Security Vulnerabilities
Doug Carson, Keysight Technologies
Cyber physical systems are dependent on a secure root of trust in silicon to ensure that hackers with physical access cannot gain control of the device or access critical data. The silicon powering these devices is delivered through a complex global supply chain which presents numerous opportunities for security vulnerabilities to be introduced at every stage in the lifecycle. In this talk we will begin with the motives for hacking hardware and how adversaries use side channel leakage and fault injection to exploit device vulnerabilities. We will then explore how these vulnerabilities can be detected at RTL and netlist levels to perform pre-silicon risk analysis. Lastly, we will outline what countermeasures can be deployed at the design stage to resilience to hardware attacks.
Biography
Doug Carson is a device security solution expert working in Edinburgh on hardware security test solutions for the Keysight Device Security Lab. During his career he as architected measurement, processing and security solutions for the full stack of telecoms covering device hardware, radio access and core network protocols. Doug has been involved in device security since 2016 as a co-author of a paper on power side channel analysis that is now the reference in the EMB3D™ framework. He currently works on market development activities for device security in Europe
In this session we will discuss the vision and roadmap of applying AI/ML to chip design and verification from what exists today to the “science fiction” future of Generative AI agents working together and orchestrated to design, verify and debug designs under the guidance of human engineers to further drive innovation beyond what we can imagine today.
Advanced RISC-V Virtualizer/Hypervisor Verification for CPU & SoC
David Kelf, Breker Verification Systems
The advent of RISC-V has presented verification teams with many new challenges. As we move towards more system-level verification and RISC-V Application Processors in general, these types of scenarios will become commonplace. This presentation will discuss a specific complex, but yet commonplace, verification challenge for any team working on a complex RISC-V core, demonstrating the types of scenarios included in the Breker RISC-V SystemVIPs. We will consider the verification of a Memory Management Unit (MMU) that includes virtualization and hypervisor operation. These scenarios need to consider both Single- and Multi-core devices along with an Input Output Memory Management Unit (IOMMU) and uncore IP interaction. The presentation will contain valuable information for any engineer or manager involved with the design of a RISC-V core or using a RISC-V core on their SoC. It will also demonstrate techniques for the verification of complex system scenarios in general.
Biography
Dave Kelf, is the CEO of Breker Verification Systems, the leader in test suite synthesis and SystemVIPs. Previously, Dave served as vice president of worldwide marketing solutions at formal verification provider OneSpin Solutions. Earlier, Kelf was president and CEO of Sigmatix, Inc. He worked in sales and marketing at Cadence Design Systems and was responsible for the Verilog and VHDL verification product lines. As vice president of marketing at Co-Design Automation and then Synopsys, Kelf oversaw the successful introduction and growth of the SystemVerilog language, before running marketing for Novas Software, noted for the Verdi product line, which became Springsoft and is now part of Synopsys. Dave holds a Bachelor of Science degree in Electronic Computer Systems from the University of Salford and a Master of Science degree in Microelectronics from Brunel University, both in the U.K., and an MBA from Boston University

Innovating for Investment: Harnessing Innovation and IP to Drive Growth
2025-07-17 16:30 - 19:00 | Bradford, CB4 0GA

Women in TechWorks – TechTalk series launch with Ras Attale (Siemens)
2025-08-27 13:00 - 13:30 | Webinar
REGISTERScalable verification for SoC: Managing complexity at scale
We’re excited to launch our Women in TechWorks network with the first in a series of inspiring and technically rich TechTalks.
Kicking off this series, we’re proud to welcome Ras Attale, Senior Hardware Engineer at Siemens, who’ll be sharing insights on Scalable Verification for SoC: Managing complexity at scale.
With the increasing complexity of modern System-on-Chip (SoC) designs, scalable verification methods are more critical than ever.
Ras will delve into approaches for managing this complexity, drawing on her experience in large-scale verification environments and sharing strategies that enable engineering teams to scale effectively and maintain quality at speed.
Ras brings a wealth of expertise, having previously contributed to the verification team at Arm, specifically on Cortex-A processors.
In addition to her current role at Siemens, she is also pursuing a Masters in Software and Systems Security at the University of Oxford, reflecting her deep commitment to continuous learning and leadership in advanced technology domains.
Join us for what promises to be a fascinating and insightful session as we launch Women in TechWorks, a platform for connection, collaboration, and visibility for women across the UK tech and engineering ecosystem.

FPGA Frontrunners: Building Resilient and Cyber Secure FPGA Systems in an Adversarial World
2025-09-10 10:00 - 14:30 | Thales, 350 Longwater Ave, Reading, RG2 6GF, United Kingdom
REGISTERSponsored by Sundance
Event Overview
In today’s hyper-connected, adversarial digital landscape, the resilience and security of Field Programmable Gate Arrays (FPGAs) are no longer just engineering challenges, they are regulatory, legal, and reputational imperatives.
A system is resilient if, and only if, there is justifiable and enduring confidence that it will function as expected, when expected. This is the baseline of trust in modern technology.But resilience alone is not enough. A system is secure when it can sustain this performance under direct adversarial pressure. When that adversary is remote, persistent, and capable of leveraging the vast cyber domain, we call this cyber security.
Security is not optional , it is mandated by law. Increasingly, regulatory bodies around the world are enforcing strict standards, and the penalties for non-compliance are not limited to fines.There is a real and growing risk of parallel criminal and civil proceedings arising from the same cyber security failure, placing immense responsibility on engineers, designers, and decision-makers to implement effective, demonstrable security controls.
This FPGA-focused event will equip you with the knowledge, techniques, and assurance frameworks necessary to design systems that are not only resilient and secure—but demonstrably so.
Who Should Attend:

FPGA Designers and Engineers
System Architects
Safety and Security Specialists
Supply Chain Professionals
Industry Regulators and Standards Bodies

Why Attend?

Gain insights from leading experts on the evolving risks and mitigation strategies
Learn how to meet functional safety and security requirements across multiple industries
Network with industry peers and potential collaborators
Participate in discussions on best practices, regulatory trends, and real-world case studies

Agenda

Time
Session

10:00
Registration

10:30
A Hardware-Accelerated Future: Pedro Machado, Nottingham University

11:00
A Defence Against Remote Power Side-Channel Attack on FPGA-based CNN: Jing He, University of Southampton

11:30
FPGA System and Device Level Security Considerations: Ian Pearson, Microchip Technology Inc.

12:00
Security Risks & Controls Across the HW-to-Cloud Stack: Mike Bartley, Alpinum Consulting

12:15
Lunch

13:00
Comparison of Embedded Cryptography Algorithms for an FPGA-Based Multi-Process: Jack Sampford, Phixos

13:30
Designing Reusable, Portable and Secure IP for FPGA: Steinn Gustafsson, Chevin Technology Limited

14:00
What do you mean Secure? Peter Davies & Sukhi Gill, Thales

14:30
Wrap Up

SpeakersIan Pearson
Principle Embedded Solutions Engineer, Microchip Technology Inc.
Ian is a Principal Field Applications Engineer at Microchip Technology Inc. He has held roles in MCU and MPU applications and also led the EU Wireless team for many years introducing Wi-Fi and Bluetooth into the embedded product lines. He has been involved with IoT since it’s inception and is an advocate of enhancing security in Connected Embedded Systems. To aid this he is active on several working groups in the IoT Security Foundation and has presented on security topics at several conferences. More recently he has returned to the FPGA space and supports Microchip clients on FPGA, SoC and Security needs across multiple market segments.
Presentation: FPGA System and Device Level Security Considerations
Creating a secure system is a complex task where multiple vulnerabilities in the design, manufacture, supply chain and maintenance of a product must be accounted for. Security is a whole of business challenge yet the foundation of a secure design relies heavily on the security capabilities of a semiconductor device and how they leverage correct implementation within the overall security posture of a product. In this presentation we will look at some of the factors involved in creating a secure FPGA, some of the threats and mitigations and how Microchip FPGA’s implement key functionality that create devices with military grade security available to all markets.
Jing He
Department of Electronics and Computer Science, University of Southampton
Jing He is a PhD candidate in the Department of Electronics and Computer Science at the University of Southampton, UK. He is a member of the Sustainable Electronic Technologies Group, and his research focuses on hardware security. Specifically, he explores lightweight, runtime defence techniques for heterogeneous systems, with an emphasis on protecting multi-tenant-based neural network accelerators.
Presentation: A Defence Against Remote Power Side-Channel Attack on FPGA-based CNN
This talk introduces a lightweight, runtime defence mechanism for FPGA-based deep learning accelerators against remote power side-channel attacks. By leveraging distributed convolution, we enhance the security of CNN execution in FPGA-based environments. The session will also present recent experimental results and discuss future research challenges.
Steinn Gustafsson
Founder, Chevin Technology
Steinn Gustafsson is the founder of Chevin Technology, a leading developer of accelerated IP for security, data protocols, and compute engines tailored to the defence, aerospace, and scientific sectors. With over 25 years of expertise in FPGA technology, Steinn has driven innovation in communication systems, ASIC design, signal processing, and digital security, and is the holder of multiple patents.
He leads a highly skilled engineering team focused on delivering secure, high-performance, and low-latency solutions, built for mission-critical environments. Steinn is deeply committed to technical excellence, strategic collaboration, and personal development, forging partnerships that enable shared success in solving complex industry challenges.
Jack Sampford
Senior Firmware Engineer, Phixos
Jack is a Senior Firmware Engineer at Phixos, with experience leading the design and implementation of multiple FPGA-based products, primarily for space and defence applications.
He has worked with Phixos for the past 5 years, providing engineering services to many industry-leading OEMs, particularly in the domain of mission- and safety-critical FPGA designs.
Presentation: Comparison of Embedded Cryptography Algorithms for an FPGA-Based Multi-Processor Design
Security within multi-processor architectures is an increasingly important consideration, with their recent usage within safety-critical systems highlighting the need for protection against potential attacks. These attacks can originate within the system, such as the possibility of a malicious program being run on one of the processors which attempts to access memory belonging to another processor. Mitigation of these types of attacks can be achieved using encryption to protect data belonging to a processor, traditionally achieved using the Advanced Encryption Standard (AES) algorithm. AES implementation on FPGA/ASIC hardware can require significant area on a device, which is a premium resource within an embedded system. In this paper, an alternative lightweight encryption algorithm, eXtended Tiny Encryption Algorithm (XTEA), is implemented and iteratively optimised on an Altera Cyclone V FPGA as part of a multi-processor design and compared to an AES implementation in terms of throughput, area utilisation, and power consumption. The obtained results show that the XTEA implementation improves throughput by 48.6%, and reduces ALM utilisation, register utilisation, and dynamic power consumption by 87.2%, 85.4%, and 86.5% respectively. This represents a significant improvement, especially in terms of area and power consumption, the most important metrics for the embedded multi-processor system this implementation is integrated into.

Designing the future: Tackling design challenges through collaboration
2025-11-06 09:00 - 17:30 | Hilton London Olympia, 380 Kensington High St, London, W14 8NL
REGISTERThank you to our Sponsors: IC Resources | Synopsys | Cadence
Women in Techworks Sponsor: MicroTECH
TechWorks DESN network aims to support the UK chip design industry by building communities of shared interest. This launch event will define new collaborative groups to address shared challenges and opportunities.
As chip complexity continues to accelerate, designers face growing challenges in architecture design, system scaling & integration and workflow. This hands-on event brings together chip architects, designers and engineers to explore real-world pain points and application trends, sharing lessons learned. The objective is to build ongoing collaboration supporting industry growth.
We will explore three contemporary themes during the event, with a plenary discussion following each one to discuss the topics raised and identify relevant actions and initiatives for DESN to curate going forward.
OUTLINE AGENDA

TIME
DETAILS

09:00
Registration

10:00
TechWorks DESN Introduction – Scene setting and objectives

10:10
THEME: The Future of Digital Design
As product roadmaps grow more demanding, the design challenges are intensifying. How are chip designs evolving architecture, workflow and methodology to stay ahead of the curve?

Nigel Toon, Executive Chairman and co-founder, Graphcore)
Mark Zwolinski, Professor, University of Southampton

11:00
Discussion and CTA

12:00
Networking Lunch

13:00
THEME: Addressing the Chiplet Challenge
To achieve vendor and substrate-independent multi-die chiplet systems, the industry must align on physical, thermal, and electrical compatibility, adopt standard packaging techniques, and develop sustainable business models. How can we make this a reality?

Yiru Zhong, Market Development Specialist, Arm
Prashant Dubey, Path Finding Researcher, Imec Cambridge UK
John Goodenough, Professor of Microelectronic Systems, University of Sheffield

14:20
Discussion and CTA

14:50
Break

15:00
THEME: Applications of Digital Design
Multiple breakthrough techniques are being driven by innovations in chip design. How can designers continue to deliver these market specific roadmaps at pace – from AI and intelligent mobility to high-performance, energy-efficient computing.

Dorian Haci, CEO and co-founder, MintNeuro
Dr Jeremy Bennett, Founder and Chief Executive, Embecosm

14:10
Discussion and CTA

16:40
Refreshments and Networking

17:30
Close

Nigel Toon
Executive Chairman and co-founder, Graphcore
Nigel is a leading AI entrepreneur and is the founder and CEO of Graphcore.ai. He sits as a Non-Executive Director on the board of UK Research and Innovation and sat on the UK Prime Minister’s Business Council. He has been recognized with numerous industry awards, being ranked #1 on Business Insider’s UK Tech 100 and named as one of the ‘Top 100 entrepreneurs in the UK’ by the Financial Times. He was awarded a Doctor of Science degree from the University of Bristol and is the author of the best-selling book How AI Thinks.
Yiru Zhong
Market Development Specialist, Arm
With more than twenty-five years in the technology sector, Yiru Zhong has led market development for emerging technologies. Yiru’s work spans product strategy, go-to-market design, and partner development, consistently aligning engineering roadmaps with market signals and operational execution. Having experienced through cycles of booms and busts in the last two decades, Yiru brings disciplined judgment about what scales and what does not.
Yiru approaches innovation from the perspective of adoption: who will use it, why it matters, and how value is realised across ecosystems. This orientation enables clear separation of durable demand from transient hype. Drawing on professional and personal experience across Asia and Europe, Yiru bridges diverse customer requirements, regulatory contexts, and supply chains to translate technical potential into commercial outcomes.
Dorian Haci
CEO & Co-Founder, MintNeuro
Dr Dorian Haci is an entrepreneur, engineer and researcher with over a decade of experience in academia and industry. As CEO and Co-Founder of MintNeuro, a spinout from Imperial College London, he is pioneering the next generation of neural implants through innovative semiconductor technologies that enable safer, smarter and more scalable brain interfaces. He also serves as an Enterprise Fellow at the Royal Academy of Engineering and a Visiting Researcher at Imperial, where he earned his PhD in microelectronics for implantable medical devices. Under his leadership, MintNeuro has secured multi-million-pound funding from the UK’s NIHR, ARIA and Innovate UK to support R&D collaborations with world-leading research institutes and medical device companies. His work focuses on advancing chip-based solutions for neurological conditions such as epilepsy, Parkinson’s and dementia.
ABSTRACT×When Chips meet the Brain: designing the next generation of neural interfaces
Digital technology has evolved through successive generations of interfaces. Mainframes brought computing into institutions, personal computers to the desk, smartphones to the hand, and wearables to the body – each step enabled by advances in semiconductor design. A similar path has shaped implantable medical technology. Early pacemakers and open-loop stimulators evolved into sensory prostheses and adaptive neuromodulators, reflecting the same semiconductor progress from transistors to integrated circuits, ASICs, and systems-on-chip.
We are now entering a 5th generation where these trajectories converge. Neural interfaces are beginning to restore communication, independence, and quality of life for people with neurological conditions, while opening new possibilities for interaction between humans and technology. Implantable systems face demanding requirements: they must be miniaturised, ultra-low-power, biocompatible, hermetically sealed, and reliable for years within a biological environment. Meeting these challenges depends on semiconductors that integrate multiple functions within millimetre-scale platforms. This requires new materials, heterogeneous integration, new architectures and computing paradigms for adaptive, closed-loop operation.
At MintNeuro, we develop semiconductor technology specifically for neural implants. Our purpose-build chip platform provides modular building blocks for functions like sensing, stimulation, and processing, enabling medical device companies and researcher to design smaller, safer, and scalable systems. By co-designing chips and devices with academic and industrial collaborators, we aim to bridge electronics and biology through shared design and engineering. This convergence defines a new frontier for semiconductor design – one where performance, safety, and collaboration meet.
John Goodenough
Professor of Microelectronic Systems, University of Sheffield
Inspiring the next generation of talented microelectronic system design engineers, researchers and educators. Driving new programs in research and curriculum that address technology and skills gaps in the Semiconductor Industry. Focus areas on the architecture, integration automation and assurance of secure, power-efficient integrated semiconductor systems.
Previously, experienced Global Technology Executive, Systems and SoC Solutions architect. With broad view across multiple Information Technology, Secure Distributed Embedded Systems, System on Chip (SoC) and Electronic Design Automation.
Dr Jeremy Bennett
Founder and Chief Executive, Embecosm
Embecosm was founded in 2008 by Dr Jeremy Bennett, an expert on hardware modeling and embedded software development. Previously Dr Bennett was Vice President of ARC International plc, following their acquisition of Tenison Design where he had been CEO and CTO.
Dr Bennett is author of the popular textbook, “Introduction to Compiling Techniques” (McGraw-Hill 1990, 1995, 2003) and holds an MA and PhD in Computer Science from Cambridge University.
Mark Zwolinski
Professor, University of Southampton
Mark Zwolinski is a Professor in the School of Electronics and Computer Science, University of Southampton. He has published over 220 journal and conference papers and 3 books. He has supervised 39 PhD students to completion.
His research interests include systems modelling, design for reliability, and heterogeneous computing. He is an Associate Editor of IEEE Transactions on VLSI. He has served on the programme committees of DATE, DAC, CODES+ISSS and ETS. He has also contributed to IEEE standards in test, VHDL and Verilog.
Mark Zwolinski is a Fellow of the IET and BCS, and a senior member of IEEE and ACM. He is a member of the Academic Accreditation Committee of the IET.
ABSTRACT×Adiabatic Logic Design for Low-Cost, Low-Energy Processing
Flexible electronics, fabricated using, for example, Thin-Film Transistors (TFTs) are a promising technology for applications such as AI/ML at the edge. Such technologies often only implement N-type transistors and thus require pull-up logic, which is very inefficient in terms of energy.
Adiabatic logic was proposed as a low power technology several decades ago. The underlying principle is that logic gates should only be turned on as they are needed and not turned off when they are active. This is achieved by using the clock, or multiple clock phases, as the power supply for logic gates. Adiabatic logic designs have been proposed that use both NMOS and PMOS transistors, but designs that use only NMOS transistors are possible. In order to achieve the promised energy efficiency, however, such circuits are very slow compared with modern CMOS technologies, which means that adiabatic logic has never achieved widespread acceptance. On the other hand, modern flexible electronics operate at relatively low frequencies. Thus, adiabatic logic may prove to be an appropriate technique for low power design in these technologies.
In this talk we will look at how adiabatic logic can be implemented in an N-type technology. We will look at some circuit designs and show that the energy-efficient clock speeds of adiabatic logic are compatible with the clock speeds achievable in flexible electronics. Nevertheless, formidable design challenges exist. Existing design tools are not compatible with adiabatic design styles. Signal paths need to be carefully balanced in order that the correct clock phases activate logic in sequence. In principle, some energy recovery is possible in adiabatic circuits, but we need to consider on-chip energy storage.
Peter Birch
Hardware Lead Engineer, Fractile
Peter Birch is a Hardware Lead Engineer at Fractile, working in the silicon team to deliver industry leading throughput and efficiency for AI inference workloads. Through past experience at VyperCore and Graphcore, he has worked with cutting-edge approaches to design, verification, and infrastructure and advocates for the use of open source tooling and methodologies in commercial ASIC development.
Prashant Dubey
Path Finding Researcher, Imec Cambridge UK
Prashant Dubey is a pathfinding researcher at Imec Cambridge UK, where he is engaged in STCO on 2nm nanosheets/forksheets and CFETS. This involves 3D and wafer level integration of TByte scale SRAMs, integrated buck converters for high voltage to low voltage vertical power delivery, back-side clock generation and routing and high-speed interconnects (petabytes/sec), for AI driven HP Compute in Data-Center applications. Prashant received his BE degree from Gorakhpur University, India in 1998 and MS research degree from IIT Delhi, on hyper-coupled ring oscillators. From 1998 to 2012 he worked for STMicroelectronics India as a Senior Design Expert, Analog & RF, where he designed embedded SRAMs and ROMs, memory and SoC DFT, analog and digital integer-N and fractional PLLs and oscillators. From 2012 to 2017 he worked for Synopsys India and led the research on low voltage SRAM architectures in 16-7nm FinFETs on write/read assist. From 2017 to 2018 he worked with Xilinx India on 3D FPGA architectures and in 2018, joined ARM Cambridge UK and then MediaTek UK where he worked on voltage droop mitigation sensors and 5G mmW, sub-100fs integrated jitter PLLs with dead-zone less 1st-order noise-shaped TDC architecture. He has produced, 25 US Patents and 14 IEEE publications.
ABSTRACT×Collaborative Ecosystem as a key enabler of AI Driven Wafer Scale Data-Centres Research
At IMEC Cambridge UK, we are currently involved in the pathfinding research of the xTCO in the domain of AI workload driven compute systems. Next-generation systems will need to handle AI models with over 100 trillion parameters or more, driving an exponential increase in compute capacity demand. The power requirements of these systems are skyrocketing. Data centres consume between 2% and 3% of the world’s electricity (approx. 400 Terawatts), according to the International Energy Agency. AI enabling data-centres can consume a massive power of at least 500MW which is enough electricity to supply two million homes. As put forth by Feryal Clark, Minister for AI, “Just like coal and steam powered our past, AI is powering the future. A significant portion of this energy is consumed by the data movement between isolated racks within data centres. Wafer-scale compute (WFC) aims to reduce this power consumption by integrating and packing compute and memory elements as close as possible. The key integration challenges in a WFC are driven by embedded memories which can be an SRAM, DRAM or any other form of emerging memories, in the orders of Terabytes, achieving latencies in the order of Petabytes/second, power delivery through vertical power delivery systems at high voltages with 500V to 1V integrated voltage converters in the order of 5 to 10Watts/mm2 and thermal extraction of a similar order. Advanced packaging is therefore another challenge due to heterogeneous integration of chiplets, which involves advanced materials and their fusion with silicon e.g. Glass, GaN etc. and is now playing a critical role in system design. Apart from advanced materials, advanced packaging also involves new technologies like TSVs and hybrid bonding and their associated modelling for design co-optimization. IMEC pathfinding research has played a vital role in advancing the industry leading technology roadmap e.g. Gate-All-Around transistors, Back-Side power delivery and continues to do so atleast with a decade margin between the conception and the productization. To convert brilliant but challenging ideas into successful products, collaborative framework is pivotal at Imec. Imec Cambridge UK has been established to enable such a collaborative framework with UK Academia, Start-ups and Industries to enable AI workload driven compute system. Our talk is aimed at the audience who are facing similar challenges in the field of wafer scale compute and see a value addition in such a collaborative framework with Imec.

IMAPS-UK: MicroTech 2026 Conference
2026-03-26 | Southampton
IMAPS-UK: MicroTech 2026 ConferenceREGISTERIMAPS-UK: MicroTech 2026 Conference at King’s Conference Centre, Hedge End, Southampton – Thursday 26th March 2026 and Heterogeneous Integration – Explained! Workshop at University of Southampton on Wednesday 25 March 2026
The IMAPS-UK MicroTech 2026 Conference on Thursday 26th March 2026 at the King’s Conference Centre, Hedge End, Southampton will focus on Driving Innovation in Semiconductor Packaging. The preliminary Conference Agenda includes state-of-the-art presentations on the advanced packaging market, the UK Semiconductor Centre, advanced packaging technologies including laser based processes, heterogeneous integration, interposers and 3D integration.
More Information and Registration: https://www.imaps.org.uk/events/microtech-2026-driving-innovation-in-semiconductor-packaging/
The Conference is complemented by a Workshop on Heterogeneous Integration – Explained! On Wednesday 25th March 2026 at the University of Southampton.
More Information and Registration: https://www.imaps.org.uk/events/heterogeneous-integration-electronics/
Please contact the IMAPS-UK Office (office@imaps.org.uk ) with any questions.

Designing the Future: Analogue Mixed Signal (AMS)
2026-03-31 09:15 - 17:20 | Regents University London, Inner Circle, Regent’s Park, London, NW1 4NS
Designing the Future: Analogue Mixed Signal (AMS)Jump to SpeakersJump to AgendaREGISTERAs complexity accelerates, designers face growing challenges in architecture, design, system scaling and workflow.
Following our Digital Design event in November, this next event brings together Analogue and Mixed Signal chip architects and designers to explore real-world pain points and application trends. During the day, we will hear from experts about the challenges and opportunities facing industry and identify how, by working together, we can support industry growth.
The event is structured around three contemporary themes, with a plenary discussion after each to discuss the topics raised and identify relevant actions going forward.
Running concurrently at the same venue, TechWorks and UKESF are hosting a Chip Design Early Careers event to bring together industry and emerging talent. The UKESF Digital Design – Early Careers track, will give companies the opportunity to engage with up to 50 next-generation chip designers (students and graduates) at the point where they are making career choices. Participants can speak directly to these early-career engineers who are keen to learn about a career in chip design, and which organisations they can join and grow with.
Overview

The future of AMS Design

How is AMS design evolving and where are we compared with pure-play digital CMOS

Design for performance, noise, and integrity across PVT
Trade-offs across process nodes and scaling limits; voltage, noise, performance, cost
Design migration, IP integration and reuse
Design flow and productivity: How can automation and AI help?
Layout challenges, routing, optimization and physical verification
Co-simulation, model abstraction and system-level verification

System architecture and Integration

Meeting system requirements while avoiding parasitics and interference is not just a circuit-level challenge. What are the current trends in system architecture and integration?

System partitioning, simulation and integration: Performance / Power / Area
Digital-analogue interfacing and interconnect. Interference mitigation and isolation
Multi-die integration: Yield reliability, Power delivery, Thermal management
Signal integrity and noise coupling in advanced packaging, 2.5D and 3D
Multi-die mixed signal chiplets and heterogeneous integration

Application drivers for AMS Design

Many emerging technologies are driving AMS innovation. What are the major application challenges pushing the frontier of analogue design today?

Future compute and AI
High-speed SerDes, Photonic interconnect, Clock & data recovery
Power delivery, voltage regulation and monitoring
Analog and in-memory compute
IoT, connectivity, med-tech and wearables
Low-noise analogue sensor integration / Energy harvesting
Physical AI / Neuromorphic compute
Low power RF

AGENDA

TIME
DETAILS

09:15
Registration

10:00
TechWorks DESN Introduction – Scene setting & objectives
Jillian Hughes, Head of Semiconductors, DESN & Charles Sturman, CEO, TechWorks

The Future of AMS Design
How is AMS design evolving and where are we compared with pure-play digital CMOS

10:10
System-First Design for High-Performance Mixed-Signal
Asad Ali, Senior IC Architect, Novamorphic

10:30
Bridging the Verification Gap Between Digital and Analog IC Design
Marcel Ahmedzai, Application Engineer Architect, Cadence

10:50
Top‑Down Approach to Mixed‑Signal Verification
Gautham Sathyan, Mixed Signal Modeling & Verification Engineer, Cirrus Logic

11:10
Verifying AMS Designs
Mike Bartley, CEO, Alpinum

11:30
Discussion and CTA

11:55
Sponsor talk: Lee Harrison, Director of Product Marketing, Tessent, Siemens EDA

12:00
Networking Lunch

System architecture and Integration
Meeting system requirements while avoiding parasitics and interference is not just a circuit-level challenge. What are the current trends in system architecture and integration?

13:00
Structured AMS migration: Device-level validation to layout closure with intelligent automation
Chris Yates, Head of AI and Machine Learning, Thalia

13:20
Revolutionizing Analog Layout Synthesis through GenAI and Machine Learning Technologies
Neel Goplan, Executive Director, Technical Product Management

13:40
Beyond 1.8 V: Enabling Robust 3.3 V Interfaces in 28 nm CMOS and 7 nm FinFET with Overvoltage Tolerant Specialty I/Os
Bart Keppens, Chief Business Development, Sofics

14:00
Discussion & Call to Action

14:25
Break

Application drivers for AMS Design
Many emerging technologies are driving AMS innovation. What are the major application challenges pushing the frontier of analogue design today?

15:10
AMS from beamforming arrays to safety critical ASICs
Konstantinos Glaros, Associate Director – Analogue IC Design, Ensilica Plc

15:20
Analog Scan: A new frontier for Mixed-signal test
Vladimir Zivkovic, Principal Product Engineer, Siemens EDA

15:40
Discussion & Call to Action

16:05
Refreshments and Networking

17:00
Close

AGENDA

09:15
Registration

10:00
TechWorks DESN Introduction – Scene setting & objectives
Jillian Hughes, Head of Semiconductors, DESN & Charles Sturman, CEO, TechWorks

The Future of AMS Design
How is AMS design evolving and where are we compared with pure-play digital CMOS

10:10
System-First Design for High-Performance Mixed-Signal
Asad Ali, Senior IC Architect, Novamorphic

10:30
Bridging the Verification Gap Between Digital and Analog IC Design
Marcel Ahmedzai, Application Engineer Architect, Cadence

10:50
Top‑Down Approach to Mixed‑Signal Verification
Gautham Sathyan, Mixed Signal Modeling & Verification Engineer, Cirrus Logic

11:10
Verifying AMS Designs
Mike Bartley, CEO, Alpinum

11:30
Discussion and CTA

11:55
Sponsor talk: Lee Harrison, Director of Product Marketing, Tessent, Siemens EDA

12:00
Networking Lunch

System architecture and Integration
Meeting system requirements while avoiding parasitics and interference is not just a circuit-level challenge. What are the current trends in system architecture and integration?

13:00
Structured AMS migration: Device-level validation to layout closure with intelligent automation
Chris Yates, Head of AI and Machine Learning, Thalia

13:20
Revolutionizing Analog Layout Synthesis through GenAI and Machine Learning Technologies
Neel Goplan, Executive Director, Technical Product Management

13:40
Beyond 1.8 V: Enabling Robust 3.3 V Interfaces in 28 nm CMOS and 7 nm FinFET with Overvoltage Tolerant Specialty I/Os
Bart Keppens, Chief Business Development, Sofics

14:00
Discussion & Call to Action

14:25
Break

Application drivers for AMS Design
Many emerging technologies are driving AMS innovation. What are the major application challenges pushing the frontier of analogue design today?

15:00
AMS from beamforming arrays to safety critical ASICs
Konstantinos Glaros, Associate Director – Analogue IC Design, Ensilica Plc

15:20
Analog Scan: A new frontier for Mixed-signal test
Vladimir Zivkovic, Principal Product Engineer, Siemens EDA

15:40
Discussion & Call to Action

16:05
Refreshments and Networking

17:00
Close

AMS SpeakersChris Yates
Head of AI and Machine Learning, Thalia
Chris Yates, Vice President of Software Engineering, leads development of EDA software for analog and mixed-signal design, optimisation and technology migration. His work applies statistical methods, mathematical optimisation and AI and machine learning to automate performance tuning and preserve circuit intent across process nodes. With a background in statistics, mathematics and artificial intelligence, he focuses on reducing design iteration time while maintaining predictability and robustness in advanced AMS flows.
Presentation×Structured AMS migration: Device-level validation to layout closure with intelligent automation
Analog and mixed signal IP migration using manual or in-house methods is rarely optimal and often slow and difficult. Y et migration remains necessary due to commercial and technical pressures. This session outlines practical ways to make migration predictable and efficient, including automated device-level comparison, early PPA assessment and intelligent layout adaptation. Drawing on recent project experience with machine learning-enhanced tools, it demonstrates how AMS engineers can preserve performance while establishing a repeatable migration methodology. The approach combines traditional analog expertise with selective automation to reduce iteration cycles and improve reliability. The discussion will show where intelligent tools can augment, not replace, engineering judgment in critical design decisions.
CloseMarcel Ahmedzai
Application Engineer Architect, Cadence
Marcel Ahmedzai is an engineering architect at Cadence with a focus on mixed signal verification and is based in Bracknell, England. Prior to Cadence he was a CAD engineer at Mitel Semiconductor and Zarlink Semiconductor. Marcel has been with Cadence for over 20 years and has a bachelor’s degree in Mathematics from the University of Hertfordshire.
Presentation×Bridging the Verification Gap Between Digital and Analog IC Design
As transistor geometries continue to shrink, modern integrated circuit designs face escalating complexity that challenges the effectiveness and efficiency of traditional verification practices. Even at the block level, the functional checks required to ensure correct behavior demand substantial time and resources, and this burden increases dramatically when scaling to chip‑level and system‑level verification. In digital design, these challenges have long been addressed through established verification methodologies, dedicated verification engineers, and standardized frameworks such as UVM. In contrast, analog and mixed‑signal (AMS) design teams often lack a comparable verification mindset, leading to late discovery of bugs, costly respins, and delays in time‑to‑market. This paper outlines the requirements and methodologies needed to elevate AMS verification to the maturity of its digital counterpart. By examining current gaps, resource impacts, and emerging best practices, we provide a structured view of how systematic AMS verification can significantly reduce design risk and improve overall product quality.
CloseMike Bartley
F0under and CEO, Alpinum
Mike started in software testing in 1988 after completing a PhD in Math, moving to semiconductor Design Verification (DV) in 1994, verifying designs (on Silicon and FPGA) going into commercial and safety-related sectors such as mobile phones, automotive, comms, cloud/data servers, and Artificial Intelligence. Mike built and managed state-of-the-art DV teams inside several companies, specialising in CPU verification.
Mike founded and grew a DV services company to 450+ engineers globally, successfully delivering services and solutions to over 50+ clients . The company was acquired by Tessolve Semiconductors in 2020 and Mike worked at Tessolve as SVP.
Mike started Alpinum in April 2025 to deliver a range of start-of-the art industry solutions.
Presentation×Verifying AMS Designs
We will be investigating strategies for verifying AMS designs from test planning, through test bench design and bring up, to test generation, closure and signoff. The talk will focus on practical, best-practice verification solutions for a variety of designs, so that the delegates can take away ideas that they can start using immediately.
CloseAsad Ali
Senior IC Architect ‑ Analogue and Mixed Signal, Novomorphic
Asad Ali, Senior IC Architect at Novomorphic, champions a System First approach to analogue and mixed-signal development. He has held leadership roles at Maxim Integrated, OnSemi, Dialog Semiconductor and LSI Logic, leading the development of high-volume RFIC, power and mixed-signal IC products from concept to production.
Presentation×System-First Design for High-Performance Mixed-Signal
In modern mixed-signal systems, the analog figure-of-merit (FOM), capturing the signal-to-noise ratio (SNR) delivered per unit power over a defined bandwidth, is a key determinant of overall system efficiency. As CMOS technology continues to scale, reduced intrinsic gain, lower supply voltages, and increased variability are fundamentally limiting the ability of traditional analog design techniques to sustain competitive FOM, directly impacting power budgets, performance headroom, and implementation cost.
This talk reframes the problem from a circuit-centric challenge to a system-level opportunity – a System First Approach. Rather than relying solely on device-level optimisation, we examine architectural and system-partitioning strategies that shift performance dependencies.
We present practical, system-driven design methodologies that mitigate technology-imposed analog limitations, enabling next-generation mixed-signal platforms to achieve aggressive performance targets while improving power efficiency, scalability, and time-to-market in line with Power-Performance-Cost objectives.
CloseKostas Glaros
Associate Director – Analogue IC Design, Ensilica Plc
Kostas Glaros is an analogue/mixed-signal technical lead with EnSilica Plc. Over the past decade he has led teams bringing multiple mixed-signal ASICs from initial concept to mass production. He focuses on medical, automotive, and industrial control applications, and has a keen interest on design methodology and tools. Kostas holds a PhD in low-power medical electronics from Imperial College London.
Presentation×AMS from beamforming arrays to safety critical ASICs
In large, multi-channel SoCs, AMS verification is essential for validating the integration of multiple analogue channels operating concurrently alongside complex digital signal processing. Safety-critical ASICs, such as industrial and automotive controllers, demand demonstrable vertical integration and traceable compliance with requirements. This talk discusses examples of AMS and DMS verification in such applications and some associated challenges.
CloseGautham Sathyan
Mixed Signal Modeling & Verification Engineer, Cirrus Logic
Gautham Sathyan is part of the Mixed-Signal Modeling and Verification group at Cirrus Logic in the Newbury office. His work spans a wide range of responsibilities, including early stage architectural modeling of mixed signal blocks, requirements definition, and establishing analog/digital boundary and the chip level schematic hierarchy. He is involved in netlisting and chip bring up DMS simulation, SystemVerilog real number modeling of low level analog cells, and to define and implement chip level AMS simulations.
With a background in analog design, Gautham particularly enjoys the challenges of modeling and debugging complex mixed signal systems. Outside of work, he spends most of his time running after his young children, though he hopes to one day start learning to play Indian music on the guitar.
×Top‑Down Approach to Mixed‑Signal Verification
A framework for first‑silicon success
Silicon Respins and late surprises can feel inevitable on complex mixed‑signal ASICs, especially when sophisticated digital control meets rich analog content. They needn’t be, argues Gautham Sathyan, in this fast‑paced, practitioner‑focused talk as he lays out a concrete framework combining a top‑down, model‑driven verification methodology with tight cross‑team alignment and disciplined use of AMS co‑simulation. 3 key CTAs from this talk :

Model early, verify continuously.
Co‑sim sparingly, where it counts.
Ship together, not in silos.

ClosePresentationVladimir Zivkovic
Principal Product Engineer, Siemens EDA
Vladimir Zivkovic is a principal product engineer for Analog Mixed-Signal and Defect-oriented Test at Siemens EDA. He graduated from the Faculty of Electrical Engineering at the University of Nis in Former Yugoslavia and obtained PhD in Electrical Engineering from the University of Twente, the Netherlands.
He has more than 20 years of industrial experience in Mixed-signal DfT, test flow automation, test coverage analysis and AMS verification. His previous affiliations include Philips Research (Netherlands), NXP Semiconductors (Netherlands), D4T Systems (small startup company, Netherlands), Nikhef/CERN (Netherlands/Switzerland), Cadence Design Systems (Scotland, UK) and Infineon (Denmark). He is program committee member of IEEE European Test Symposium (ETS) and provided significant contribution during the development of IEEE 2427 standard for Analog Defect Modeling and Coverage. He is also vice chair of IEEE P1687.2 (Analog Test Access standardization) working group.
Presentation×Analog Scan: A new frontier for Mixed-signal test
Developing tests for designs with mixed-signal circuits has always been a bottleneck during IC product sign-off, regardless of the application. This talk presents a revolutionary approach for creating efficient manufacturing mixed-signal tests that reduce test costs and test escapes. The methodology is called analog scan and requires DfT of a circuit-under-test (CUT) to inject stimulus signals and observe responses. The inserted circuitry is not placed in series with signal propagation paths, and it is turned off in the mission mode. The control and output of the DfT circuitry is connected to test data registers (TDRs), typically placed outside the mixed-signal block under test.
Analog scan methodology brings multiple benefits. First, there is a massive decrease of test cost, since analog scan tests run orders of magnitude faster than a large majority of spec-based tests on ATE. Analog defect simulation also runs much faster than for spec-based tests. With appropriate automation, top-level test development is also significantly accelerated. Defect coverage figures achieved with analog scan are usually higher than those obtained with functional tests. Lastly, analog scan facilitates diagnosis of field returns.
Bart Keppens
Chief Business Development, Sofics
Bart Keppens received an engineering degree in electronics in 1996 and started his career at imec in Belgium. From 2002 he joined Sarnoff Europe, solving on-chip ESD related problems for customers worldwide. After a management buy-out in June 2009, Sarnoff Europe became ‘SOFICS – Solutions for ICs’ where Bart is responsible for global business development. Bart (co-) authored more than 40 peer-reviewed published articles on ESD protection.
Presentation×Beyond 1.8 V: Enabling Robust 3.3 V Interfaces in 28 nm CMOS and 7 nm FinFET with Overvoltage Tolerant Specialty I/Os
As CMOS nodes scale, designers face a widening gap between core capabilities and system-level requirements. While foundry GPIOs in FinFET and GAA processes typically top out at 1.8V, many applications still demand 3.3V “Over-Voltage Tolerant” (OVT) interfaces for legacy compatibility and robust system integration. Conversely, the rise of chiplet architectures introduces the opposite challenge: Die-to-Die (D2D) interfaces that must operate at specialty voltages below the typical GPIO range (1V or lower) to minimize power and maximize speed.
This presentation explores the design and ESD protection of these specialty interfaces. We examine the “3.3V in a 1.8V process” dilemma, focusing on stacking techniques to maintain Safe Operating Area (SOA) during power sequencing and transient events. We then pivot to the unique requirements of chiplet interconnects. Unlike standard I/Os, D2D interfaces require: (a) Specialized ESD: Traditional >2kV HBM protection is often overkill for D2D, introducing excessive parasitic capacitance that limits bandwidth. (b) Thin-Oxide Integration: To achieve high speeds, D2D circuits utilize sensitive thin-oxide transistors that are easily damaged without custom ESD clamps. (c) Area Efficiency: With thousands of required connections, standard I/O pads consume prohibitive silicon area.
Attendees will gain a practical framework for specifying and verifying both higher and lower voltage specialty I/Os, with an emphasis on co-designing circuits and ESD to optimize PPA in modern, heterogeneous systems.
Lee Harrison
Director of Product Marketing, Tessent, Siemens EDA
Lee Harrison is Director, Product Marketing, with Siemens Tessent Division. He has over 25 years of industry experience working with Siemens Tessent DFT products, with a focus on safety and security. Lee Received his BEng in MicroElectronic Engineering from Brunel University London in 1996. Lee presents regularly at industry conferences such as DAC, ITC, VTS, ETS, and DATE.
Neel Goplan
Executive Director, Technical Product Management, Synopsys
Neel Gopalan is an Executive Director, in the Products and Market group. Neel leads Technical Product Management for AMS tools including Custom Compiler, PrimeSim and Characterization. Neel has been with Synopsys for the last 20 years; during this time he has been part of Custom Compiler Product Engineering team. He was an integral part of the team that built Custom Compiler along with all the collaterals needed for Custom Design. Neel and his team built industry’s 1st iPDK, which is now the standard for PDKs in the industry. Neel now leads Analog Design Migration, ASO and Layout Synthesis. Prior to Synopsys, Neel worked for Cadence for 5 years
Presentation×Revolutionizing Analog Layout Synthesis through GenAI and Machine Learning Technologies
The rapid advancement of semiconductor technology necessitates innovative approaches to Analog Layout Synthesis, a critical aspect in circuit design for FinFET and GAA nodes. This presentation introduces Industry’s First transformative potential of Generative AI (GenAI) and Machine Learning (ML) in automating and optimizing the analog layout process. We will discuss how GenAI can generate high-quality layout designs by learning from vast datasets of existing designs, while ML algorithms enhance the efficiency of design creation and predictions. Furthermore, we will delve into the role of AI in facilitating intelligent decision-making throughout the design process, enabling adaptive responses to design constraints and objectives. By integrating these cutting-edge technologies, we aim to significantly reduce design time, improve layout quality, and foster innovation in analog circuit design. This presentation will provide insights into the methodologies employed, the challenges encountered, and the future directions of analog layout synthesis in the context of AI-driven advancements
×Meet the Students

From RTL and verification to open-source silicon tapeouts, these exceptional students are already making an impact in digital chip design
James Ashie Kotey | Electronics & Computer Engineering, University of Sheffield | IC Engineering Intern at EnSilica
James has contributed to commercial ASIC projects in RTL design and functional verification, and has led three open-source silicon projects from concept to tapeout using open-source EDA tools and PDKs.
Carys MacIntyre | Robotics Engineering (Integrated Master’s), University of Bath | Hardware Intern at Siemens EDA (Tessent Embedded Analytics)
Currently on a 12-month placement in digital RTL verification, Carys is gaining hands-on verification experience alongside her master’s studies.
Charlie Teare | Mechatronics & Robotic Systems (BEng with Year in Industry) , University of Liverpool
Following a placement with EnSilica’s digital design team, Charlie continues collaborating with industry while completing his final year project focused on a fabric/interconnect generator.
Ronit Ravi | Electronic Engineering, Imperial College London
Now in his final year, Ronit previously completed a placement in Design Verification at Siemens EDA and continues to collaborate during his master’s research.
This event provides students and early-career designers with direct exposure to professionals in digital chip design , embedding their learning and offering tangible inspiration for careers in the UK semiconductor sector.

Digital Design Early Careers SpeakersHaydn Povey
Founder and CEO, SCI Semiconductor
With over 30 years experience in the technology domain Haydn has unparalleled experience in microprocessor IP, cyber security, and real world cyber-physical systems.
Having led the introduction of Arm Cortex-M processors he subsequently led the Processor Divisions security technologies, including TrustZone & SecurCore.
He is a founder board member of the IoT Security Foundation.
Dave Sanders
Associate Fellow, Rolls-Royce
Dave Sanders is an Associate Fellow at Rolls-Royce specialising in the development of complex electronic hardware. He has 28 years of experience working in the electronics industry, with 26 of those developing the safety critical microprocessors that form the heart of the Rolls-Royce control systems for both aerospace and non-aerospace applications.
Dave is a member of the European DO254 Users Group since 2012 and has contributed to various regulation working groups including co-authoring AMC 20-152A. He became a Fellow of the IET in 2018 and was awarded the Rolls-Royce Controls Gold Innovation Award in 2015 in recognition of the successful development of the sixth-generation safety critical microprocessor, which has already accumulated over 30 million fault free flying hours.
In his spare time, Dave is a keen runner and currently Lichfield Running Club Secretary.
Michael O’Sullivan
Engineering director, Cadence
Michael O’Sullivan is an engineering director at Cadence with a focus on verification and is based in Edinburgh, Scotland. Michael has been with Cadence for over 27 years with various roles in sales, marketing and design services.
Prior to Cadence he was a design engineer at S3 Group in Dublin, Ireland and at Philips in Eindhoven, The Netherlands. Michael has an Masters of Engineering Science from the National University of Ireland.
Loay Qteet
Staff Application Engineer, Synopsys
Loay Qteet, Applications Engineering, Staff Engineer at Synopsys, with six years of experience in the Electronic Design Automation (EDA) field. He specializes in physical design, RTLIIGDS flow development, and EDA applications of Implementation and AI. Loay has played a key role in supporting various customer, helping them to achieve their goals effectively and ensuring that Synopsys products meet their evolving requirements.
Catriona Wright
Co-founder, Chipletti
Catriona Wright is co-founder of Chipletti, a Cambridge-based fabless semiconductor startup developing AI accelerators for physical AI systems that require low power, high performance real-time operation within tight SWaP-C constraints. She works across strategy, partnerships, and operations while helping translate emerging AI compute needs into practical hardware solutions.
Read More
Catriona has more than 25 years of experience delivering complex semiconductor products from concept through to production. Her career spans digital design, program leadership, and scaling multidisciplinary teams to deliver advanced silicon. Before founding Chipletti, she held roles at both start-ups and large companies including Riverlane, DisplayLink, Cambridge Semiconductor, TTPCom and Nortel Networks, leading IC development programmes and coordinating cross-functional engineering teams.
She holds a First Class MEng in Electrical and Electronic Engineering from the University of Edinburgh and an MBA from The Open University. Catriona is passionate about building strong deep tech teams and helping grow the semiconductor ecosystem in the UK. She is also active in outreach, running coding clubs for primary school students and encouraging more young people – particularly girls – to explore engineering.

Moderator

Matt Cossins
Ecosystem Development Manager, Arm
Matt Cossins is an Ecosystem Development Manager in Arm’s AI and Developer Platforms group, where he supports the adoption of Arm-powered AI compute platforms through developer education, enablement, and collaboration between industry and academia.
Read More
An alumnus of the UKESF programme, he holds an MEng in Electrical and Electronic Engineering from the University of Nottingham, where his thesis focused on neuromorphic AI. He previously held engineering roles at Capgemini, delivering software and embedded research projects for multiple clients, and at Cambridge-based cellXica, where he worked on embedded and RTL design for software-defined radio in 5G communications.
Matt is a recipient of awards from organisations including the IET, UKESF, and Electronics Weekly, and mentors engineering students through the Arkwright Scholarships Trust.

Raj Gawera
Chief Operating Officer, UK Semiconductor Centre
Raj has over 30 years of experience in the semiconductor field having held senior technical and commercial roles in semiconductor organisations spanning IP, Fabless and IDM business models. He is now COO of the newly formed UK Semiconductor Centre – with an ambitious plan to strengthen the UK semiconductor ecosystem and grow international partnerships.
Read More
In his early career, Raj was part of initial IEEE 802.11 team to define first WLAN standard in 1996 – a technology which has now shipped many billions of units. Raj also helped pioneer the first 3G data transmissions working with Motorola and others to demonstrate one of the first 3G video calls at the 3GSM show in 1998 – many years before 3G licences were awarded.
Raj was a founder member of 3G technology startup UbiNetics (1999), that successfully exited in 2005 for over $120m USD. As part of that deal, Raj joined CSR and ultimately took the role of VP Marketing where he was part of the team that acquired SiRF Technologies for $136m (2009) to add GPS technology to CSR portfolio. In 2012, he helped sell CSR’s handset business to Samsung in a deal worth $310m for 310 staff. As part of Samsung, Raj was promoted to VP heading up the SCSC division leading the silicon and software development for Samsung’s chipsets for over a decade, providing connectivity technology that shipped in hundreds of millions of Samsung products.
Raj has held a number of board positions including Chair of Cambridge Wireless and NED for CSA Catapult bringing experience and advice on the global semiconductor market.

Mahdieh Ghoddusi
Director of Delivery, UKESF
Mahdieh Ghoddusi
Director of Delivery, UKESF
Prof. Nick McKeown

FPGA Frontrunners Event
2026-04-16 10:00 - 14:30 | Microchip, 720 Wharfedale Road, Winnersh, RG41 5TP
FPGA Frontrunner EventREGISTERCLICK HERE to find out more about the FPGA FrontrunnersField Programmable Gate Arrays (FPGAs) play a critical role in modern electronic systems, powering applications that range from everyday consumer products to mission-critical infrastructure. Their ability to be customized and reconfigured after deployment makes them uniquely valuable in fast-moving technology environments. At the same time, this adaptability introduces distinct security challenges that must be carefully addressed.
Because FPGAs can be reprogrammed in the field, they present a broader attack surface than fixed-function hardware. Threats targeting configuration data, intellectual property, firmware integrity, and runtime behavior can compromise not only the device itself, but also the larger systems that rely on it. As FPGAs are increasingly used to support advanced workloads—including data-intensive and intelligent processing—security risks continue to grow in both scope and impact.
Effective FPGA security extends beyond physical protection. It encompasses the full lifecycle and ecosystem surrounding the device, including design tools, bitstreams, firmware, software interfaces, and data flows. In systems that incorporate adaptive or AI-assisted functionality, ensuring trust, integrity, and resilience across this ecosystem is especially critical.
This event explores the evolving landscape of FPGA security, highlighting emerging threats, recent advances, and proven mitigation strategies. Through expert insights and real-world case studies, the program aims to equip engineers, researchers, and security professionals with practical guidance for securing FPGA-based systems today and in
knowledge, techniques, and assurance frameworks necessary to design systems that are not only resilient and secure—but demonstrably so.
Who Should Attend
FPGA Designers and EngineersSystem ArchitectsSafety and Security SpecialistsSupply Chain ProfessionalsIndustry Regulators and Standards Bodies
Why Attend?

Gain insights from leading experts on the evolving risks and mitigation strategies
Learn how to meet functional safety and security requirements across multiple industries
Network with industry peers and potential collaborators
Participate in discussions on best practices, regulatory trends, and real-world case studies

Outline Agenda

Time
Details

10:00
Registration

10:30
Microchip Secure FPGA’sIan PearsonPr. ESE, Microchip

11:00
A Visual Demonstration of True Random Numbers from a Quantum ComputerPhill J PaynePrincipal Digital Design Engineer, Novomorphic

11:30
Are FPGAs unique for security?Martin ThompsonSenior Technical Specialist, ZF Engineering Solutions

12:00
Beyond Bitstream Encryption: FPGA Security for High-Assurance SystemsDaniel TeeSenior Firmware (FPGA) Engineer, Leonardo

12:30
Networking Lunch

13:30
Overview of prEN50767 : CRA Vertical Standard for FPGA/ASICPeter TrottStaff FAE, Microchip

14:00
Hardware-Rooted Bitstream SecurityMans AhmadianChief Innovation Officer, Sundance

14:30
Wrap Up

14:45
Close

Phill J Payne, Principal Digital Design Engineer, Novomorphic
Presentation: A Visual Demonstration of True Random Numbers from a Quantum Computer
True randomness is one of those things everyone assumes they have… right up until security, trust, or assurance actually matters.
This session reveals a practical way to pull physical entropy from a real quantum computer and inject it into FPGA and embedded systems as a usable, engineering-grade input. You’ll see quantum behaviour turned into something tangible and immediate — a live “quantum dice” demonstrator that makes the invisible visible — and you’ll learn why this matters far beyond novelty.
We’ll explore what changes when your randomness isn’t “noisy enough” pseudo-random, but rooted in genuine physical uncertainty, and how that can reshape thinking around key generation, nonces, reseeding, and trusted system design. A live comparison between simulation and real quantum hardware draws a clear line between “looks random” and “is random”.
If you build secure edge systems and care about trust boundaries, this will change how you think about entropy.
profile×Phill J Payne
Phill J Payne is Principal Digital Design Engineer at Novomorphic, specialising in secure, real-time FPGA and embedded architectures for edge AI. He is developing convolution acceleration and a modular hardware fabric that composes reconfigurable pipelines, reduces memory pressure, and delivers high-performance vision and inference at the edge. Across 26 years, Phill has turned novel architectural ideas into deployable systems under tight power, latency, throughput, and reliability constraints, with deep experience in security-grade FPGA development and signal-processing workloads. Previously, he delivered end-to-end FPGA firmware and software for advanced systems, including a patented communications technique designed to operate in contested jamming environments, later acquired by a major defence prime. He also built specialised training systems used in preparation for the London 2012 Olympic Games, translating complex engineering into practical tools.
Martin Thompson, Senior Technical Specialist, ZF Engineering Solutions
Presentation: Are FPGAs unique for security?

In this talk we will investigate the degree to which systems containing programmable logic (including FPGAs) can be considered “unique” in their security requirements and implementation options, when compared to more conventional microcontroller and desktop processor systems.
We will briefly define what we mean by “security” in this context (both in terms of market requirements and attacker motivations) and what primitives can be used to achieve it. A review of the variety of potential attacks will be presented and we will spend some time on the peculiarities of FPGA-based systems by comparing them directly with other implementation strategies. Finally, we will conclude with an answer to the question posed in the title.
profile×Martin Thompson
Martin Thompson is a Senior Technical Specialist at ZF Engineering Solutions. He has spent over 30 years developing systems and algorithms for products in the automotive and aerospace domains. He enjoys working across the full range of software and electronics disciplines, from desktop algorithm development to microcontroller, DSP and FPGA code as well as electronic design, PCB layout (and when the need arises, soldering!). He specialises in optimisations of whole electronic systems, based on a detailed understanding of the trade-offs across multiple domains. Particular highlights have included the development of very low-cost FPGA-based imaging and radar-systems.
Since 2015, Martin has been heavily involved in the cybersecurity of embedded systems and is currently the technical leader of an penetration-testing team with an embedded-system focus. He contributes to the Internet of Things Security Foundation Assurance Framework, the Automotive Threat Matrix, and is a member of the MITRE hardware CWE SIG and the CWE-RTL working group. Finally, he spends some of his time researching novel side-channel attacks in pursuit of a PhD, with the University of Durham.
Mans Ahmadian, Chief Innovation Officer, Sundance

Presentation: Hardware-Rooted Bitstream Security and Secure Manufacturing Workflow

A Defense-Grade Implementation Using PolarFire FPGA on Sundance PCIe104N Platform As FPGAs become central to mission-critical defense and aerospace systems, the security challenge has shifted. It is no longer enough to protect configuration data in the fi eld; we must also secure it during manufacturing, programming, testing, and across the entire supply chain. When production is distributed across multiple facilities and third-party partners, the FPGA bitstream becomes a high-value target, vulnerable to interception, overbuilding, hardware substitution, or reverse engineering. This talk presents a defence-grade secure provisioning workflow implemented on the Sundance PCIe104N platform, built around the PolarFire MPF500T FPGA, and explains how it establishes trust from silicon to system deployment.
Read More
At the heart of this approach is hardware-rooted security. PolarFire devices generate a unique, silicon-derived identity using Physically Unclonable Functions (PUFs), meaning that no two FPGAs are electrically identical and no identity can be copied or cloned. During secure provisioning, this identity is validated before any sensitive key material is transferred. The customer’s encrypted bitstream and User Encryption Key are generated inside their own trusted environment and securely delivered for programming using Microchip’s Secure Production Programming Solution. If authentication fails at any stage, such as in a dummy FPGA impersonation attempt, the process stops immediately. No keys are exposed, and no firmware is released. What this workflow ultimately provides is confidence. Confidence that the hardware being programmed is genuine. Confidence that only the approved number of boards can ever be provisioned. Confidence that the bitstream cannot be intercepted, modified, or extracted through side-channel attacks. By combining controlled manufacturing, independent validation, hardware security modules, authenticated encryption, and built-in DPA countermeasures, Sundance ensures customers receive fully tested, securely programmed boards, without any risk of supply-chain compromise or intellectual property leakage. Today, I will walk you through how this architecture works and why it sets a scalable model for secure FPGA manufacturing.

profile×Mans Ahmadian
Mans Ahmadian serves as the Chief Innovation Officer at Sundance, where he leads the architecture of next-generation, high-density AI Systems-on-Modules (SoMs). In this role, he directs the design of specialized AI Engines and systems otimized for low-power, high-throughput inference in rugged environments. He is instrumental in bridging the gap between AI frameworks and SundanceDSP hardware. Additionally, his work ensures the reliability of autonomous Edge AI platforms in mission-critical settings by optimizing SWaP (Size, Weight, and Power) solutions and integrating safety-critical, “fail-safe” R&D workflows.
Throughout his career, he has been granted numerous patents for his innovations in image processing, advanced camera systems and imaging sensor operations. His technical and commercial achievements have earned him several prestigious honors, including the IET (Institute of Engineering and Technology) Innovation Award in software development, the SMART::SCOTLAND Innovation Award, and a Business Plan Competition win. These accolades are supported by a robust academic foundation, including a PhD in Medical Image Processing, an MSc in Biomedical/Medical Engineering, and a BSc in Electronics from The University of Edinburgh, and postgraduate certificates in Health Data Science and Big Data and AI.
Daniel Tee, Senior Firmware (FPGA) Engineer, Leonardo

Presentation: Beyond Bitstream Encryption: FPGA Security for High-Assurance Systems

Field programmable gate arrays (FPGAs) are increasingly deployed in systems where failure or compromise is not an option – from defence and aerospace to critical infrastructure and advanced industrial platforms. In these high assurance environments, security requirements extend beyond the protections normally offered by device vendors. Engineers must consider the broader context of threats, deployment conditions, and system level risk.
Read More
This presentation explores the evolving landscape of FPGA security and outlines practical considerations for designing and deploying secure programmable logic systems. It introduces the principles that shape high assurance engineering, highlights common security challenges unique to reconfigurable hardware, and discusses methods for establishing trust from initial configuration through runtime operation. The talk also touches on modern approaches to isolation, secure execution, and configuration protection, alongside emerging trends that FPGA developers should be aware of as threats and technologies continue to advance.
Attendees will gain a clearer understanding of how to think about security in FPGA based systems, along with a set of concepts and design patterns that can be adapted to a wide range of high assurance applications.

profile×Daniel Tee
Daniel Tee is a Senior Firmware (FPGA) Engineer at Leonardo, working within the product security team. He joined Leonardo as a graduate in 2022 after completing an integrated MEng in Electronics and Computer Science at the University of Edinburgh, where he focused on a number of cybersecurity modules in his final year. Daniel now applies his interest in hardware security to developing robust FPGA‑based security solutions for customer‑driven, mission‑critical applications.
Ian Pearson, Pr. ESE, Microchip Technology Inc.

Presentation: Leveraging Microchip Secure FPGAs

The foundation of a secure end product lies in the right choice of components. CRA requires a ‘Secure by Design’ approach to product development and support throughout the lifecycle. Microchip FPGA’s have a long history of secure FPGA’s designed to meet the most demanding of military applications but available to all
profile×Ian Pearson
Ian Pearson is a Principle Embedded Solutions Engineer with Microchip Technology covering FPGA, Security and IoT. He is also the chair of the IoT Security Foundation – Security Assurance Framework Working Group.
Peter Trott, Staff FAE, Microchip Technology Inc.

Presentation: Overview of prEN50767 : CRA Vertical Standard for FPGA/ASIC

The EU CRA requirements can be met via a presumption of conformity using horizontal and vertical harmonised standards. These standards are in development and will release very close to the enforcement date. In this session we will give some insight into what is coming in the vertical standard for FPGA/ASIC. The prEN50767 standard provides the requirements for FPGA/ASIC vendors to meet the Important Class I categorisation of FPGA/ASIC in the EU CRA.
profile×Peter Trott
Peter Trott is a Staff Applications engineer at Microchip with over 30yrs experience in the FPGA sector. He has extensive experience in both military and industrial design using FPGA’s. Peter is also a key member of the EU TC47x WG4 Trusted Silicon work group for FPGA/ASIC who are creating the prEN50767 harmonised standard relative to the Important Class I FPGA/ASIC with security features

29th World Micromachining Summit
2026-06-14 - 2026-06-17 | Southampton

Women in TechWorks: Engineering Intelligently
2026-06-17 09:15 - 17:20 | Arm, Cambridge, CB1 9NJ
Women in TechWorks Launch EventRegisterConnecting Talent
Women in TechWorks comes together in person for the first time — bringing the community to the heart of the UK’s technology ecosystem.
Hosted at Arm, this landmark event builds on the program created through tech talks, town halls and fireside chats.
Why Attend?
TechWorks sits at the centre of the UK’s leading technology communities — semiconductors, embedded systems, cybersecurity, future compute and AI.
On 17 June, we bring together the full spectrum of talent across these sectors for a day of:

Inspiring talks from exceptional women in industry
Panel discussions spanning leadership, innovation and visibility
Networking across career stages — from early careers to founders and C-suite leaders

Who It’s For
This event is open to everyone.
While it showcases outstanding women shaping UK technology, it’s designed for everyone , and be part of a stronger, more inclusive tech ecosystem.
From Momentum to Action
Women in TechWorks is focused on:

Leadership
Mentorship
Visibility

This first face-to-face event brings those pillars to life
Join us for a day that connects people, ideas and opportunity.

Verification & Semiconductors Futures Conference UK 2026
2026-06-23 | University of Reading, Whiteknights PO Box 217, Reading, Berkshire, RG6 6AH, United Kingdom
Verification Futures UK 2026, co-located with Semiconductors Futures 2026 co-organised by Tessolve and Alpinum.
The conference continues its strong tradition of delivering a unique blend of conference presentations, exhibitions, training, and industry networking sessions focused on the challenges faced in hardware and software verification. The event remains an important forum for end-users to define their verification challenges and collaborate with engineers, researchers, and vendors to shape practical solutions. In 2026, Verification Futures continues to strengthen its core emphasis on verification methodologies, DV tools, and engineering workflows, including areas such as formal methods for complex SoCs, CPU & RISC-V verification, open-source and licence-free verification tools, AI in design verification (AI in DV), verification planning and coverage, and HW/SW co-verification.
Semiconductors Futures 2026 brings together the semiconductor community, covering AI/ML in IP & SoC design, AI’s impact on EDA and workflows, FPGA & mixed-signal, with a focus on the automotive, data centre, and AI products. New tracks consider emerging technologies such as quantum computing, photonics, and chiplets, as well as startups and investments. We expect 50+ engineering students to attend a separate session.
DetailsSimon Southwell
Systems Consultant
Wyvern Semiconductors
×Simon Southwell
Complex protocol modelling with OSVVM co-simulation, exploring the PCIe VC
A look at OSVVM co-simulation features and their use for constructing complex protocol verification component using PCIe as an example. It looks at the integration of the PCIe GEN1/GEN2 C model from the presenter’s pcieVHost project, using OSVVM’s co-simulation capabilities, to construct an OSVVM compatible Verification Component (VC), used like any other VHDL based VC, but with additional features, to drive 3rd party PCIe IP. An example of driving Altera’s Cyclone V Hard IP for PCI Express is discussed.
Biography
Engineer with 35+ years in R&D, with experience in ASIC design, FPGA, and embedded software development. Currently working on developing open-source IP in areas such as co-simulation and system modelling. A collaborator on the OSVVM project, adding and supporting its co-simulation capabilities and developing verification IP.
Areas of experiences include logic IP for both ASIC and FPGA, logic verification, HPC, processor systems, networking (802.3 and proprietary), embedded software, co-simulation technology, software modelling of SoC systems, data compression logic, PCIe endpoint design, cellular (3G and 4G), wireless (802.11 and 802.15.4). Joint or sole author on several logic IP related patents.
DetailsRojalin Mishra
Lead Verification Engineer
River Lane
×Rojalin Mishra
From Qubits to Confidence: Verifying Quantum Error Correction
Quantum error correction (QEC) introduces fundamentally new challenges for verification, where probabilistic behaviour and correlated errors break many conventional methodologies. This talk explores how we adapt verification strategies to this domain, including designing testbenches for probabilistic measurement data, modelling spatially and temporally correlated noise, and defining meaningful coverage for error correction circuits.
Through real debugging case studies, we highlight subtle failure modes unique to quantum systems—such as silent corruption during syndrome extraction—and discuss approaches to validating decoder behaviour across complex syndrome spaces. We also examine how verification can be performed under realistic noise distributions to build confidence in system-level reliability.
Bio: I am an Electronics and Communications engineer with over a decade of experience in ASIC/FPGA verification, specialising in complex digital systems and verification methodologies. I currently serve as a Lead Verification Engineer, driving UVM-based verification for Quantum Error Correction within the rapidly evolving field of Quantum Computing.
DetailsSteinn Gustafsson
Founder
Chevin Technology
×Steinn Gustafsson
Presentation Title: Complex protocol modelling with OSVVM co-simulation, exploring the PCIe VC
A look at OSVVM co-simulation features and their use for constructing complex protocol verification component using PCIe as an example. It looks at the integration of the PCIe GEN1/GEN2 C model from the presenter’s pcieVHost project, using OSVVM’s co-simulation capabilities, to construct an OSVVM compatible Verification Component (VC), used like any other VHDL based VC, but with additional features, to drive 3rd party PCIe IP. An example of driving Altera’s Cyclone V Hard IP for PCI Express is discussed.
Bio: Engineer with 35+ years in R&D, with experience in ASIC design, FPGA, and embedded software development. Currently working on developing open-source IP in areas such as co-simulation and system modelling. A collaborator on the OSVVM project, adding and supporting its co-simulation capabilities and developing verification IP.
Areas of experiences include logic IP for both ASIC and FPGA, logic verification, HPC, processor systems, networking (802.3 and proprietary), embedded software, co-simulation technology, software modelling of SoC systems, data compression logic, PCIe endpoint design, cellular (3G and 4G), wireless (802.11 and 802.15.4). Joint or sole author on several logic IP related patents.
DetailsYassine Eben Aimine
Siemens
×Yassine Eben Aimine
Yassine has more than 20 years’ experience in the EDA industry. Throughout his professional career, Yassine has partnered with design and verification engineers to deploy the latest technologies in EDA tooling in the areas of design for test, functional verification, and functional safety.
DetailsPhill J Payne
Principal Digital Design Engineer
Novomorphic
×Phill J Payne
Phill J Payne is Principal Digital Design Engineer at Novomorphic, specialising in secure, real-time FPGA and embedded architectures for edge AI. He is developing convolution acceleration and a modular hardware fabric that composes reconfigurable pipelines, reduces memory pressure, and delivers high-performance vision and inference at the edge. Across 26 years, Phill has turned novel architectural ideas into deployable systems under tight power, latency, throughput, and reliability constraints, with deep experience in security-grade FPGA development and signal-processing workloads. Previously, he delivered end-to-end FPGA firmware and software for advanced systems, including a patented communications technique designed to operate in contested jamming environments, later acquired by a major defence prime. He also built specialised training systems used in preparation for the London 2012 Olympic Games, translating complex engineering into practical tools.
DetailsGavin Lofts
Field Applications Engineer
Altera
×Gavin Lofts
Gavin Lofts is a Field Applications Engineer at Altera with 20+ years of experience in hardware, embedded software, and FPGA design. He has worked on systems ranging from biosensors to radio.
Presentation: CI/CD and Git for Modern FPGA Development

Women in TechWorks: From Qubits to Confidence: Verifying Quantum Error Correction
2026-08-20 14:00 - 15:00 | Webinar

TechWorks Semiconductors to Systems Summit 2026
2026-08-26
