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DTSTART;VALUE=DATE:20250701
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SUMMARY:Verification Futures 2025 - FEATURING tracks from DESN and TechWorks AI
DESCRIPTION:Verification Futures 2025RegisterJoin us at the verification futures event taking place on 1st July 2025 in Reading.\nAs part of the expanded agenda for Verification Futures UK 2025\, a brand-new Design Track will debut\, hosted by the connected networks of Techworks (Techworks AI and DESN). This track will focus on the latest advances in AI-enabled IP\, next-generation SoC and semiconductor design\, and breakthrough technologies transforming the electronics landscape. \nThe Verification Futures conference has always provided a unique blend of presentations\, exhibitions\, and industry networking — offering a platform for end-users to define verification challenges and collaborate with engineers and vendors to create solutions. In 2025\, Verification Futures UK is expanding to reflect the evolving landscape of semiconductor design\, with a strong focus on AI/ML applications in IP/SoC\, FPGA\, and Mixed Signal designs. \nAttendees will gain access to cutting-edge technical content and expert presentations in \n• AI-Enhanced Semiconductor and IP Design\n• Next-Generation IP Architectures and Verification Strategies\n• Innovative Design Methodologies and Flows\n• Emerging and Breakthrough Technologies\n• Design for AI/ML Acceleration and Edge Computing< \nWhy Attend the Design Track? \n• Gain technical insights from industry-leading engineers\, architects\, and researchers\n• Learn from cutting-edge research and case studies addressing real-world design and verification challenges\n• Network with 250+ onsite professionals and 1\,000+ virtual participants across the semiconductor and verification ecosystem\n• Engage with emerging talent from the UK Electronics Skills Foundation (UKESF) showcasing their work\n• Collaborate with UK’s leading semiconductor startups through SiCatalyst UK\n• Be inspired by keynote addresses from visionaries\, including Sean Redmond \n \n\nDesign Track Agenda \n\n\n\nTime\nName\nTalk Title\n\n\n\n\n11:30\nMartin Zeller\, Dream Chip\nThree approaches to cope with rising ASIC complexity\n\n\n11:50\nGareth Richards\, Techworks\nTechWorks-AI and TAIBOM – Engineering Trustable AI\n\n\n12:10\nJames Lewis\, Red Semiconductor\nRISC-V: Innovating Within An Established Architecture\n\n\nBreak\n\n\n\n\n13:30\nBradley Geden\nThe Era of Agentic Engineering – Roadmap to Level 5\n\n\n14:00\nJohn Wickerson\, Imperial College London\nTesting and verifying the tools of hardware design\n\n\n14:20\nDoug Carsen\n\n\n\n14:40\nSpeaker TBC\n\n\n\n15:00\nSpeaker TBC\n\n\n\n15:20\nCristian Sestito\, University of Edinburgh\nTrIM: An Efficient Systolic Array for Convolutional Neural Networks\n\n\n15:40\nSpeaker TBC\n\n\n\n\n\n\nIntroducing New Tracks! \nVerification Futures 2025 will feature exciting new additions: \n• IP Stream: Explore the latest trends and solutions in intellectual property (IP) verification.\n• FPGA Track: Explore FPGA verification techniques\n• Mixed Signal\n• Verification Projects using Open Source/License-Free Tools \nRegistration \nRegister now to become a part of this event in-person or online. \n Click here to register.  \nTesting and verifying the tools of hardware design\nJohn Wickerson\, Senior Lecturer\, Imperial College London \nHardware engineers rely on several tools to build hardware\, such as high-level synthesis tools to convert C code into Verilog\, logic synthesis tools to convert Verilog into netlists\, and so on until they end up with a design that can be implemented on an FPGA or fabricated on an ASIC. Mistakes are difficult and expensive to rectify\, so engineers routinely use formal equivalence checkers to double-check that each transformation is correct. All these tools are critical pieces of software infrastructure and are highly trusted… but are they trustworthy? At Imperial\, we have been developing new techniques for testing and verifying hardware design tools. We have found bugs in all of the tools we have tested\, even the formal equivalence checkers. Some of these bugs cause the tools simply to crash; others are more sinister\, causing the tools to produce incorrect results. We are also prototyping new hardware design tools that come with a mechanically checked proof of their own correctness and thus promise the highest standard of reliability. The work is led by my current and former PhD students Yann Herklotz\, Quentin Corradi\, and Michalis Pardalos\, and is also in collaboration with George Constantinides\, Alastair Donaldson\, Emiliano Morini\, and Laura Pozzi. \nBiography \nJohn Wickerson is a Senior Lecturer in the Department of Electrical and Electronic Engineering at Imperial College London. His research is at the intersection of programming languages and hardware design \nTechWorks-AI and TAIBOM – Engineering Trustable AI\nGareth Richards\, Network Manager\, TechWorks AI \nOutline of the new Techworks-AI community\, bringing together members\, regardless of sector of operation\, who have a common interest in AI/ML technology\, developments and applications and an overview of the TAIBOM. \nBiography \nGareth has over 35 years’ experience leading the design and development of electronic systems used by millions of people every day in the UK\, United States and Japan\, including highly secure EAL4+ point of sale products used \nTesting and verifying the tools of hardware design\nJohn Wickerson\, Imperial College London \nHardware engineers rely on several tools to build hardware\, such as high-level synthesis tools to convert C code into Verilog\, logic synthesis tools to convert Verilog into netlists\, and so on until they end up with a design that can be implemented on an FPGA or fabricated on an ASIC. Mistakes are difficult and expensive to rectify\, so engineers routinely use formal equivalence checkers to double-check that each transformation is correct. All these tools are critical pieces of software infrastructure and are highly trusted… but are they trustworthy? At Imperial\, we have been developing new techniques for testing and verifying hardware design tools. We have found bugs in all of the tools we have tested\, even the formal equivalence checkers. Some of these bugs cause the tools simply to crash; others are more sinister\, causing the tools to produce incorrect results. We are also prototyping new hardware design tools that come with a mechanically checked proof of their own correctness and thus promise the highest standard of reliability. The work is led by my current and former PhD students Yann Herklotz\, Quentin Corradi\, and Michalis Pardalos\, and is also in collaboration with George Constantinides\, Alastair Donaldson\, Emiliano Morini\, and Laura Pozzi. \nBiography \nJohn Wickerson is a Senior Lecturer in the Department of Electrical and Electronic Engineering at Imperial College London. His research is at the intersection of programming languages and hardware design \nRethinking chip(let) design for next generation ADAS applications \nMartin Zeller\, Dream Chip \nThree approaches to cope with rising ASIC complexity. \nBiography \nMartin is responsible for the SoC development at Dreamchip\, a Tessolve company. \nHe has a diploma in electrical engineering from Leibniz University of Hannover and a business diploma from the University of Hagen. For more than 25 years he has developed ASICs and architectures\, mainly for video coding and imaging; starting with Infineon’s first mobile phone camera\, later enhancing Silicon Image’s HDMI interface ASICs to TV processor SoCs. In the last years he mainly worked on latest generation ADAS SoCs for several major players in the automotive industry. \nIn 2010 Martin joined DreamChip Technologies GmbH as the Head of SoC Design. In 2016 his team designed the world’s first 22nm ADAS SoC based on ARM’s Cortex A53 application processor and ARM’s Cortex R5 lockstep safety core as a platform for further developments. In the last years\, several automotive SoCs based on this platform have been built by Dreamchip. \nIn 2022 and 2023 new generations of Dreamchip’s platform have been taped out. \nMartin also worked as a trainer for ARM Cortex processor integration. \nThe Era of Agentic Engineering – Roadmap to Level 5\nBradley Geden\, Synopsys \nWe are now in the era of pervasive intelligence from voice assistants\, advanced robotics\, drone-based delivery to autonomous cars\, and chatbots. This begs the question\, how are we doing in design verification? Design verification is one of the most expensive and time-consuming activities for any chip design. Moreover\, every year the cost of design verification grows exponentially and despite that ½ of design re-spins are caused by functional or logic bugs. \nWith the advent of Large Language Models (LLM) and Generative Pre-Trained Transformer (GPT) models\, what are the possibilities in design verification? \nIn this session we will discuss the vision and roadmap of applying AI/ML to chip design and verification from what exists today to the “science fiction” future of Generative AI agents working together and orchestrated to design\, verify and debug designs under the guidance of human engineers to further drive innovation beyond what we can imagine today. \nBiography \nBradley Geden is the Senior Director of Product Management for Verification Software at Synopsys based in Sunnyvale\, CA. He has over 20 years of experience in the EDA industry covering a broad range of domains from Custom Design\, Circuit Simulation\, Digital Implementation and Verification in both Product Management and Sales Roles at Synopsys and Siemens EDA. Prior to entering the world of EDA he was an Analog Mixed-Signal Design Engineer working on Energy Measurement and Wireless Communication Chips. In his spare time\, Bradley enjoys travelling and exploring the world with his wife\, preferably on a sail boat! \nIn this session we will discuss the vision and roadmap of applying AI/ML to chip design and verification from what exists today to the “science fiction” future of Generative AI agents working together and orchestrated to design\, verify and debug designs under the guidance of human engineers to further drive innovation beyond what we can imagine today. \nPre-silicon Identification of Security Vulnerabilities\nDoug Carson\, Keysight Technologies \nCyber physical systems are dependent on a secure root of trust in silicon to ensure that hackers with physical access cannot gain control of the device or access critical data. The silicon powering these devices is delivered through a complex global supply chain which presents numerous opportunities for security vulnerabilities to be introduced at every stage in the lifecycle. In this talk we will begin with the motives for hacking hardware and how adversaries use side channel leakage and fault injection to exploit device vulnerabilities. We will then explore how these vulnerabilities can be detected at RTL and netlist levels to perform pre-silicon risk analysis. Lastly\, we will outline what countermeasures can be deployed at the design stage to resilience to hardware attacks. \nBiography \nDoug Carson is a device security solution expert working in Edinburgh on hardware security test solutions for the Keysight Device Security Lab. During his career he as architected measurement\, processing and security solutions for the full stack of telecoms covering device hardware\, radio access and core network protocols. Doug has been involved in device security since 2016 as a co-author of a paper on power side channel analysis that is now the reference in the EMB3D™ framework. He currently works on market development activities for device security in Europe \nIn this session we will discuss the vision and roadmap of applying AI/ML to chip design and verification from what exists today to the “science fiction” future of Generative AI agents working together and orchestrated to design\, verify and debug designs under the guidance of human engineers to further drive innovation beyond what we can imagine today. \nAdvanced RISC-V Virtualizer/Hypervisor Verification for CPU & SoC\nDavid Kelf\, Breker Verification Systems \nThe advent of RISC-V has presented verification teams with many new challenges. As we move towards more system-level verification and RISC-V Application Processors in general\, these types of scenarios will become commonplace. This presentation will discuss a specific complex\, but yet commonplace\, verification challenge for any team working on a complex RISC-V core\, demonstrating the types of scenarios included in the Breker RISC-V SystemVIPs. We will consider the verification of a Memory Management Unit (MMU) that includes virtualization and hypervisor operation. These scenarios need to consider both Single- and Multi-core devices along with an Input Output Memory Management Unit (IOMMU) and uncore IP interaction. The presentation will contain valuable information for any engineer or manager involved with the design of a RISC-V core or using a RISC-V core on their SoC. It will also demonstrate techniques for the verification of complex system scenarios in general. \nBiography \nDave Kelf\, is the CEO of Breker Verification Systems\, the leader in test suite synthesis and SystemVIPs. Previously\, Dave served as vice president of worldwide marketing solutions at formal verification provider OneSpin Solutions. Earlier\, Kelf was president and CEO of Sigmatix\, Inc. He worked in sales and marketing at Cadence Design Systems and was responsible for the Verilog and VHDL verification product lines. As vice president of marketing at Co-Design Automation and then Synopsys\, Kelf oversaw the successful introduction and growth of the SystemVerilog language\, before running marketing for Novas Software\, noted for the Verdi product line\, which became Springsoft and is now part of Synopsys. Dave holds a Bachelor of Science degree in Electronic Computer Systems from the University of Salford and a Master of Science degree in Microelectronics from Brunel University\, both in the U.K.\, and an MBA from Boston University
URL:https://desn.org.uk/event/verification-futures-2025/
CATEGORIES:DESN Partnered Event
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BEGIN:VEVENT
DTSTART;TZID=Europe/London:20250717T163000
DTEND;TZID=Europe/London:20250717T190000
DTSTAMP:20250624T130321Z
CREATED:20250624T130105Z
LAST-MODIFIED:20250624T130321Z
UID:22924-1752769800-1752778800@desn.org.uk
SUMMARY:Innovating for Investment: Harnessing Innovation and IP to Drive Growth
DESCRIPTION:
URL:https://eip.com/uk/latest/events/innovating-for-investment-how-the-right-approach-to-innovation-and-ip-can-help-grow-and-secure-investment#new_tab
LOCATION:Bradford\, CB4 0GA
CATEGORIES:DESN Promoted Event
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BEGIN:VEVENT
DTSTART;TZID=Europe/London:20250827T130000
DTEND;TZID=Europe/London:20250827T133000
DTSTAMP:20250818T145917Z
CREATED:20250811T113338Z
LAST-MODIFIED:20250818T145917Z
UID:23012-1756299600-1756301400@desn.org.uk
SUMMARY:Women in TechWorks – TechTalk series launch with Ras Attale (Siemens)
DESCRIPTION:REGISTERScalable verification for SoC: Managing complexity at scale\nWe’re excited to launch our Women in TechWorks network with the first in a series of inspiring and technically rich TechTalks. \nKicking off this series\, we’re proud to welcome Ras Attale\, Senior Hardware Engineer at Siemens\, who’ll be sharing insights on Scalable Verification for SoC: Managing complexity at scale. \nWith the increasing complexity of modern System-on-Chip (SoC) designs\, scalable verification methods are more critical than ever. \nRas will delve into approaches for managing this complexity\, drawing on her experience in large-scale verification environments and sharing strategies that enable engineering teams to scale effectively and maintain quality at speed. \nRas brings a wealth of expertise\, having previously contributed to the verification team at Arm\, specifically on Cortex-A processors. \nIn addition to her current role at Siemens\, she is also pursuing a Masters in Software and Systems Security at the University of Oxford\, reflecting her deep commitment to continuous learning and leadership in advanced technology domains. \nJoin us for what promises to be a fascinating and insightful session as we launch Women in TechWorks\, a platform for connection\, collaboration\, and visibility for women across the UK tech and engineering ecosystem.
URL:https://desn.org.uk/event/women-in-techworks-techtalk-series-launch-with-ras-attale-siemens/
LOCATION:Webinar
CATEGORIES:TechWorks Event
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BEGIN:VEVENT
DTSTART;TZID=Europe/London:20250910T100000
DTEND;TZID=Europe/London:20250910T143000
DTSTAMP:20250905T095706Z
CREATED:20250708T120907Z
LAST-MODIFIED:20250905T095706Z
UID:22934-1757498400-1757514600@desn.org.uk
SUMMARY:FPGA Frontrunners:  Building Resilient and Cyber Secure FPGA Systems in an Adversarial World
DESCRIPTION:REGISTERSponsored by Sundance\nEvent Overview\nIn today’s hyper-connected\, adversarial digital landscape\, the resilience and security of Field Programmable Gate Arrays (FPGAs) are no longer just engineering challenges\, they are regulatory\, legal\, and reputational imperatives. \nA system is resilient if\, and only if\, there is justifiable and enduring confidence that it will function as expected\, when expected. This is the baseline of trust in modern technology.But resilience alone is not enough. A system is secure when it can sustain this performance under direct adversarial pressure. When that adversary is remote\, persistent\, and capable of leveraging the vast cyber domain\, we call this cyber security. \nSecurity is not optional \, it is mandated by law. Increasingly\, regulatory bodies around the world are enforcing strict standards\, and the penalties for non-compliance are not limited to fines.There is a real and growing risk of parallel criminal and civil proceedings arising from the same cyber security failure\, placing immense responsibility on engineers\, designers\, and decision-makers to implement effective\, demonstrable security controls. \nThis FPGA-focused event will equip you with the knowledge\, techniques\, and assurance frameworks necessary to design systems that are not only resilient and secure—but demonstrably so. \nWho Should Attend: \n\nFPGA Designers and Engineers\nSystem Architects\nSafety and Security Specialists\nSupply Chain Professionals\nIndustry Regulators and Standards Bodies\n\nWhy Attend? \n\nGain insights from leading experts on the evolving risks and mitigation strategies\nLearn how to meet functional safety and security requirements across multiple industries\nNetwork with industry peers and potential collaborators\nParticipate in discussions on best practices\, regulatory trends\, and real-world case studies\n\nAgenda \n\n\n\n\n\nTime\nSession\n\n\n\n\n10:00\nRegistration\n\n\n10:30\nA Hardware-Accelerated Future: Pedro Machado\, Nottingham University\n\n\n11:00\nA Defence Against Remote Power Side-Channel Attack on FPGA-based CNN: Jing He\, University of Southampton\n\n\n11:30\nFPGA System and Device Level Security Considerations: Ian Pearson\, Microchip Technology Inc.\n\n\n12:00\nSecurity Risks & Controls Across the HW-to-Cloud Stack: Mike Bartley\, Alpinum Consulting\n\n\n12:15\nLunch\n\n\n13:00\nComparison of Embedded Cryptography Algorithms for an FPGA-Based Multi-Process: Jack Sampford\, Phixos\n\n\n13:30\nDesigning Reusable\, Portable and Secure IP for FPGA: Steinn Gustafsson\, Chevin Technology Limited\n\n\n14:00\nWhat do you mean Secure? Peter Davies & Sukhi Gill\, Thales\n\n\n14:30\nWrap Up\n\n\n\n\nSpeakersIan Pearson\nPrinciple Embedded Solutions Engineer\, Microchip Technology Inc. \nIan is a Principal Field Applications Engineer at Microchip Technology Inc. He has held roles in MCU and MPU applications and also led the EU Wireless team for many years introducing Wi-Fi and Bluetooth into the embedded product lines. He has been involved with IoT since it’s inception and is an advocate of enhancing security in Connected Embedded Systems. To aid this he is active on several working groups in the IoT Security Foundation and has presented on security topics at several conferences. More recently he has returned to the FPGA space and supports Microchip clients on FPGA\, SoC and Security needs across multiple market segments. \nPresentation: FPGA System and Device Level Security Considerations \nCreating a secure system is a complex task where multiple vulnerabilities in the design\, manufacture\, supply chain and maintenance of a product must be accounted for. Security is a whole of business challenge yet the foundation of a secure design relies heavily on the security capabilities of a semiconductor device and how they leverage correct implementation within the overall security posture of a product. In this presentation we will look at some of the factors involved in creating a secure FPGA\, some of the threats and mitigations and how Microchip FPGA’s implement key functionality that create devices with military grade security available to all markets. \nJing He\nDepartment of Electronics and Computer Science\, University of Southampton\nJing He is a PhD candidate in the Department of Electronics and Computer Science at the University of Southampton\, UK. He is a member of the Sustainable Electronic Technologies Group\, and his research focuses on hardware security. Specifically\, he explores lightweight\, runtime defence techniques for heterogeneous systems\, with an emphasis on protecting multi-tenant-based neural network accelerators. \nPresentation: A Defence Against Remote Power Side-Channel Attack on FPGA-based CNN \nThis talk introduces a lightweight\, runtime defence mechanism for FPGA-based deep learning accelerators against remote power side-channel attacks. By leveraging distributed convolution\, we enhance the security of CNN execution in FPGA-based environments. The session will also present recent experimental results and discuss future research challenges. \nSteinn Gustafsson\nFounder\, Chevin Technology\nSteinn Gustafsson is the founder of Chevin Technology\, a leading developer of accelerated IP for security\, data protocols\, and compute engines tailored to the defence\, aerospace\, and scientific sectors. With over 25 years of expertise in FPGA technology\, Steinn has driven innovation in communication systems\, ASIC design\, signal processing\, and digital security\, and is the holder of multiple patents. \nHe leads a highly skilled engineering team focused on delivering secure\, high-performance\, and low-latency solutions\, built for mission-critical environments. Steinn is deeply committed to technical excellence\, strategic collaboration\, and personal development\, forging partnerships that enable shared success in solving complex industry challenges. \nJack Sampford\nSenior Firmware Engineer\, Phixos\nJack is a Senior Firmware Engineer at Phixos\, with experience leading the design and implementation of multiple FPGA-based products\, primarily for space and defence applications. \nHe has worked with Phixos for the past 5 years\, providing engineering services to many industry-leading OEMs\, particularly in the domain of mission- and safety-critical FPGA designs. \nPresentation: Comparison of Embedded Cryptography Algorithms for an FPGA-Based Multi-Processor Design \nSecurity within multi-processor architectures is an increasingly important consideration\, with their recent usage within safety-critical systems highlighting the need for protection against potential attacks. These attacks can originate within the system\, such as the possibility of a malicious program being run on one of the processors which attempts to access memory belonging to another processor. Mitigation of these types of attacks can be achieved using encryption to protect data belonging to a processor\, traditionally achieved using the Advanced Encryption Standard (AES) algorithm. AES implementation on FPGA/ASIC hardware can require significant area on a device\, which is a premium resource within an embedded system. In this paper\, an alternative lightweight encryption algorithm\, eXtended Tiny Encryption Algorithm (XTEA)\, is implemented and iteratively optimised on an Altera Cyclone V FPGA as part of a multi-processor design and compared to an AES implementation in terms of throughput\, area utilisation\, and power consumption. The obtained results show that the XTEA implementation improves throughput by 48.6%\, and reduces ALM utilisation\, register utilisation\, and dynamic power consumption by 87.2%\, 85.4%\, and 86.5% respectively. This represents a significant improvement\, especially in terms of area and power consumption\, the most important metrics for the embedded multi-processor system this implementation is integrated into.
URL:https://desn.org.uk/event/building-resilient-and-cyber-secure-fpga-systems-in-an-adversarial-world/
LOCATION:Thales\, 350 Longwater Ave\, Reading\, RG2 6GF\, United Kingdom
CATEGORIES:DESN Event
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DTSTART;TZID=Europe/London:20251106T090000
DTEND;TZID=Europe/London:20251106T173000
DTSTAMP:20260119T093201Z
CREATED:20250818T092753Z
LAST-MODIFIED:20260119T093201Z
UID:23065-1762419600-1762450200@desn.org.uk
SUMMARY:Designing the future: Tackling design challenges through collaboration
DESCRIPTION:REGISTERThank you to our Sponsors:  IC Resources   |    Synopsys   |   Cadence\nWomen in Techworks Sponsor: MicroTECH\nTechWorks DESN network aims to support the UK chip design industry by building communities of shared interest. This launch event will define new collaborative groups to address shared challenges and opportunities.\nAs chip complexity continues to accelerate\, designers face growing challenges in architecture design\, system scaling & integration and workflow. This hands-on event brings together chip architects\, designers and engineers to explore real-world pain points and application trends\, sharing lessons learned. The objective is to build ongoing collaboration supporting industry growth. \nWe will explore three contemporary themes during the event\, with a plenary discussion following each one to discuss the topics raised and identify relevant actions and initiatives for DESN to curate going forward. \nOUTLINE AGENDA \n\n\n\n\n\nTIME\nDETAILS\n\n\n\n\n09:00\nRegistration\n\n\n10:00\nTechWorks DESN Introduction – Scene setting and objectives\n\n\n10:10\nTHEME: The Future of Digital Design \nAs product roadmaps grow more demanding\, the design challenges are intensifying. How are chip designs evolving architecture\, workflow and methodology to stay ahead of the curve? \n\nNigel Toon\, Executive Chairman and co-founder\, Graphcore) \nMark Zwolinski\, Professor\, University of Southampton\n\n\n\n\n11:00\nDiscussion and CTA\n\n\n12:00\nNetworking Lunch\n\n\n13:00\nTHEME: Addressing the Chiplet Challenge \nTo achieve vendor and substrate-independent multi-die chiplet systems\, the industry must align on physical\, thermal\, and electrical compatibility\, adopt standard packaging techniques\, and develop sustainable business models. How can we make this a reality? \n\nYiru Zhong\, Market Development Specialist\, Arm\nPrashant Dubey\, Path Finding Researcher\, Imec Cambridge UK\nJohn Goodenough\, Professor of Microelectronic Systems\, University of Sheffield\n\n\n\n\n14:20\nDiscussion and CTA\n\n\n14:50\nBreak\n\n\n15:00\nTHEME: Applications of Digital Design \nMultiple breakthrough techniques are being driven by innovations in chip design. How can designers continue to deliver these market specific roadmaps at pace – from AI and intelligent mobility to high-performance\, energy-efficient computing. \n\nDorian Haci\, CEO and co-founder\, MintNeuro\nDr Jeremy Bennett\, Founder and Chief Executive\, Embecosm\n\n\n\n\n14:10\nDiscussion and CTA\n\n\n16:40\nRefreshments and Networking\n\n\n17:30\nClose\n\n\n\n\nNigel Toon\nExecutive Chairman and co-founder\, Graphcore \nNigel is a leading AI entrepreneur and is the founder and CEO of Graphcore.ai.  He sits as a Non-Executive Director on the board of UK Research and Innovation and sat on the UK Prime Minister’s Business Council. He has been recognized with numerous industry awards\, being ranked #1 on Business Insider’s UK Tech 100 and named as one of the ‘Top 100 entrepreneurs in the UK’ by the Financial Times. He was awarded a Doctor of Science degree from the University of Bristol and is the author of the best-selling book How AI Thinks. \nYiru Zhong\nMarket Development Specialist\, Arm \nWith more than twenty-five years in the technology sector\, Yiru Zhong has led market development for emerging technologies. Yiru’s work spans product strategy\, go-to-market design\, and partner development\, consistently aligning engineering roadmaps with market signals and operational execution. Having experienced through cycles of booms and busts in the last two decades\, Yiru brings disciplined judgment about what scales and what does not.\nYiru approaches innovation from the perspective of adoption: who will use it\, why it matters\, and how value is realised across ecosystems. This orientation enables clear separation of durable demand from transient hype. Drawing on professional and personal experience across Asia and Europe\, Yiru bridges diverse customer requirements\, regulatory contexts\, and supply chains to translate technical potential into commercial outcomes. \nDorian Haci\nCEO & Co-Founder\, MintNeuro \nDr Dorian Haci is an entrepreneur\, engineer and researcher with over a decade of experience in academia and industry. As CEO and Co-Founder of MintNeuro\, a spinout from Imperial College London\, he is pioneering the next generation of neural implants through innovative semiconductor technologies that enable safer\, smarter and more scalable brain interfaces. He also serves as an Enterprise Fellow at the Royal Academy of Engineering and a Visiting Researcher at Imperial\, where he earned his PhD in microelectronics for implantable medical devices. Under his leadership\, MintNeuro has secured multi-million-pound funding from the UK’s NIHR\, ARIA and Innovate UK to support R&D collaborations with world-leading research institutes and medical device companies. His work focuses on advancing chip-based solutions for neurological conditions such as epilepsy\, Parkinson’s and dementia. \nABSTRACT×When Chips meet the Brain: designing the next generation of neural interfaces\nDigital technology has evolved through successive generations of interfaces. Mainframes brought computing into institutions\, personal computers to the desk\, smartphones to the hand\, and wearables to the body – each step enabled by advances in semiconductor design. A similar path has shaped implantable medical technology. Early pacemakers and open-loop stimulators evolved into sensory prostheses and adaptive neuromodulators\, reflecting the same semiconductor progress from transistors to integrated circuits\, ASICs\, and systems-on-chip. \nWe are now entering a 5th generation where these trajectories converge. Neural interfaces are beginning to restore communication\, independence\, and quality of life for people with neurological conditions\, while opening new possibilities for interaction between humans and technology. Implantable systems face demanding requirements: they must be miniaturised\, ultra-low-power\, biocompatible\, hermetically sealed\, and reliable for years within a biological environment. Meeting these challenges depends on semiconductors that integrate multiple functions within millimetre-scale platforms. This requires new materials\, heterogeneous integration\, new architectures and computing paradigms for adaptive\, closed-loop operation. \nAt MintNeuro\, we develop semiconductor technology specifically for neural implants. Our purpose-build chip platform provides modular building blocks for functions like sensing\, stimulation\, and processing\, enabling medical device companies and researcher to design smaller\, safer\, and scalable systems. By co-designing chips and devices with academic and industrial collaborators\, we aim to bridge electronics and biology through shared design and engineering. This convergence defines a new frontier for semiconductor design – one where performance\, safety\, and collaboration meet. \nJohn Goodenough\nProfessor of Microelectronic Systems\, University of Sheffield \nInspiring the next generation of talented microelectronic system design engineers\, researchers and educators. Driving new programs in research and curriculum that address technology and skills gaps in the Semiconductor Industry. Focus areas on the architecture\, integration automation and assurance of secure\, power-efficient integrated semiconductor systems. \nPreviously\, experienced Global Technology Executive\, Systems and SoC Solutions architect. With broad view across multiple Information Technology\, Secure Distributed Embedded Systems\, System on Chip (SoC) and Electronic Design Automation. \nDr Jeremy Bennett\nFounder and Chief Executive\, Embecosm \nEmbecosm was founded in 2008 by Dr Jeremy Bennett\, an expert on hardware modeling and embedded software development. Previously Dr Bennett was Vice President of ARC International plc\, following their acquisition of Tenison Design where he had been CEO and CTO. \nDr Bennett is author of the popular textbook\, “Introduction to Compiling Techniques” (McGraw-Hill 1990\, 1995\, 2003) and holds an MA and PhD in Computer Science from Cambridge University. \nMark Zwolinski\nProfessor\, University of Southampton \nMark Zwolinski is a Professor in the School of Electronics and Computer Science\, University of Southampton. He has published over 220 journal and conference papers and 3 books. He has supervised 39 PhD students to completion. \nHis research interests include systems modelling\, design for reliability\, and heterogeneous computing. He is an Associate Editor of IEEE Transactions on VLSI. He has served on the programme committees of DATE\, DAC\, CODES+ISSS and ETS. He has also contributed to IEEE standards in test\, VHDL and Verilog. \nMark Zwolinski is a Fellow of the IET and BCS\, and a senior member of IEEE and ACM. He is a member of the Academic Accreditation Committee of the IET. \nABSTRACT×Adiabatic Logic Design for Low-Cost\, Low-Energy Processing\nFlexible electronics\, fabricated using\, for example\, Thin-Film Transistors (TFTs) are a promising technology for applications such as AI/ML at the edge. Such technologies often only implement N-type transistors and thus require pull-up logic\, which is very inefficient in terms of energy. \nAdiabatic logic was proposed as a low power technology several decades ago. The underlying principle is that logic gates should only be turned on as they are needed and not turned off when they are active. This is achieved by using the clock\, or multiple clock phases\, as the power supply for logic gates. Adiabatic logic designs have been proposed that use both NMOS and PMOS transistors\, but designs that use only NMOS transistors are possible. In order to achieve the promised energy efficiency\, however\, such circuits are very slow compared with modern CMOS technologies\, which means that adiabatic logic has never achieved widespread acceptance. On the other hand\, modern flexible electronics operate at relatively low frequencies. Thus\, adiabatic logic may prove to be an appropriate technique for low power design in these technologies. \nIn this talk we will look at how adiabatic logic can be implemented in an N-type technology. We will look at some circuit designs and show that the energy-efficient clock speeds of adiabatic logic are compatible with the clock speeds achievable in flexible electronics. Nevertheless\, formidable design challenges exist. Existing design tools are not compatible with adiabatic design styles. Signal paths need to be carefully balanced in order that the correct clock phases activate logic in sequence. In principle\, some energy recovery is possible in adiabatic circuits\, but we need to consider on-chip energy storage. \nPeter Birch\nHardware Lead Engineer\, Fractile \nPeter Birch is a Hardware Lead Engineer at Fractile\, working in the silicon team to deliver industry leading throughput and efficiency for AI inference workloads. Through past experience at VyperCore and Graphcore\, he has worked with cutting-edge approaches to design\, verification\, and infrastructure and advocates for the use of open source tooling and methodologies in commercial ASIC development. \nPrashant Dubey\nPath Finding Researcher\, Imec Cambridge UK \nPrashant Dubey is a pathfinding researcher at Imec Cambridge UK\, where he is engaged in STCO on 2nm nanosheets/forksheets and CFETS. This involves 3D and wafer level integration of TByte scale SRAMs\, integrated buck converters for high voltage to low voltage vertical power delivery\, back-side clock generation and routing and high-speed interconnects (petabytes/sec)\, for AI driven HP Compute in Data-Center applications. Prashant received his BE degree from Gorakhpur University\, India in 1998 and MS research degree from IIT Delhi\, on hyper-coupled ring oscillators. From 1998 to 2012 he worked for STMicroelectronics India as a Senior Design Expert\, Analog & RF\, where he designed embedded SRAMs and ROMs\, memory and SoC DFT\, analog and digital integer-N and fractional PLLs and oscillators. From 2012 to 2017 he worked for Synopsys India and led the research on low voltage SRAM architectures in 16-7nm FinFETs on write/read assist. From 2017 to 2018 he worked with Xilinx India on 3D FPGA architectures and in 2018\, joined ARM Cambridge UK and then MediaTek UK where he worked on voltage droop mitigation sensors and 5G mmW\, sub-100fs integrated jitter PLLs with dead-zone less 1st-order noise-shaped TDC architecture. He has produced\, 25 US Patents and 14 IEEE publications. \nABSTRACT×Collaborative Ecosystem as a key enabler of AI Driven Wafer Scale Data-Centres Research\nAt IMEC Cambridge UK\, we are currently involved in the pathfinding research of the xTCO in the domain of AI workload driven compute systems. Next-generation systems will need to handle AI models with over 100 trillion parameters or more\, driving an exponential increase in compute capacity demand. The power requirements of these systems are skyrocketing. Data centres consume between 2% and 3% of the world’s electricity (approx. 400 Terawatts)\, according to the International Energy Agency. AI enabling data-centres can consume a massive power of at least 500MW which is enough electricity to supply two million homes. As put forth by Feryal Clark\, Minister for AI\, “Just like coal and steam powered our past\, AI is powering the future. A significant portion of this energy is consumed by the data movement between isolated racks within data centres. Wafer-scale compute (WFC) aims to reduce this power consumption by integrating and packing compute and memory elements as close as possible. The key integration challenges in a WFC are driven by embedded memories which can be an SRAM\, DRAM or any other form of emerging memories\, in the orders of Terabytes\, achieving latencies in the order of Petabytes/second\, power delivery through vertical power delivery systems at high voltages with 500V to 1V integrated voltage converters in the order of 5 to 10Watts/mm2 and thermal extraction of a similar order. Advanced packaging is therefore another challenge due to heterogeneous integration of chiplets\, which involves advanced materials and their fusion with silicon e.g. Glass\, GaN etc. and is now playing a critical role in system design. Apart from advanced materials\, advanced packaging also involves new technologies like TSVs and hybrid bonding and their associated modelling for design co-optimization. IMEC pathfinding research has played a vital role in advancing the industry leading technology roadmap e.g. Gate-All-Around transistors\, Back-Side power delivery and continues to do so atleast with a decade margin between the conception and the productization. To convert brilliant but challenging ideas into successful products\, collaborative framework is pivotal at Imec. Imec Cambridge UK has been established to enable such a collaborative framework with UK Academia\, Start-ups and Industries to enable AI workload driven compute system. Our talk is aimed at the audience who are facing similar challenges in the field of wafer scale compute and see a value addition in such a collaborative framework with Imec.
URL:https://desn.org.uk/event/designing-the-future-tackling-design-challenges-through-collaboration/
LOCATION:Hilton London Olympia\, 380 Kensington High St\, London\, W14 8NL
CATEGORIES:Past Event
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DTEND;VALUE=DATE:20260327
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SUMMARY:IMAPS-UK: MicroTech 2026 Conference
DESCRIPTION:IMAPS-UK: MicroTech 2026 ConferenceREGISTERIMAPS-UK: MicroTech 2026 Conference at King’s Conference Centre\, Hedge End\, Southampton – Thursday 26th March 2026 and Heterogeneous Integration – Explained! Workshop at University of Southampton on Wednesday 25 March 2026 \nThe IMAPS-UK MicroTech 2026 Conference on Thursday 26th March 2026 at the King’s Conference Centre\, Hedge End\, Southampton will focus on Driving Innovation in Semiconductor Packaging. The preliminary Conference Agenda includes state-of-the-art presentations on the advanced packaging market\, the UK Semiconductor Centre\, advanced packaging technologies including laser based processes\, heterogeneous integration\, interposers and 3D integration. \nMore Information and Registration: https://www.imaps.org.uk/events/microtech-2026-driving-innovation-in-semiconductor-packaging/ \nThe Conference is complemented by a Workshop on Heterogeneous Integration – Explained! On Wednesday 25th March 2026 at the University of Southampton. \nMore Information and Registration: https://www.imaps.org.uk/events/heterogeneous-integration-electronics/ \nPlease contact the IMAPS-UK Office (office@imaps.org.uk ) with any questions.
URL:https://desn.org.uk/event/imaps-uk-microtech-2026-conference/
LOCATION:Southampton
CATEGORIES:DESN Promoted Event
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SUMMARY:Designing the Future: Analogue Mixed Signal (AMS)
DESCRIPTION:Designing the Future: Analogue Mixed Signal (AMS)Jump to SpeakersJump to AgendaREGISTERAs complexity accelerates\, designers face growing challenges in architecture\, design\, system scaling and workflow.  \nFollowing our Digital Design event in November\, this next event brings together Analogue and Mixed Signal chip architects and designers to explore real-world pain points and application trends. During the day\, we will hear from experts about the challenges and opportunities facing industry and identify how\, by working together\, we can support industry growth.  \nThe event is structured around three contemporary themes\, with a plenary discussion after each to discuss the topics raised and identify relevant actions going forward.  \nRunning concurrently at the same venue\, TechWorks and UKESF are hosting a Chip Design Early Careers event to bring together industry and emerging talent. The UKESF Digital Design – Early Careers track\, will give companies the opportunity to engage with up to 50 next-generation chip designers (students and graduates) at the point where they are making career choices. Participants can speak directly to these early-career engineers who are keen to learn about a career in chip design\, and which organisations they can join and grow with.  \nOverview  \n\nThe future of AMS Design\n\nHow is AMS design evolving and where are we compared with pure-play digital CMOS  \n\nDesign for performance\, noise\, and integrity across PVT \nTrade-offs across process nodes and scaling limits; voltage\, noise\, performance\, cost \nDesign migration\, IP integration and reuse \nDesign flow and productivity: How can automation and AI help? \nLayout challenges\, routing\, optimization and physical verification \nCo-simulation\, model abstraction and system-level verification \n\n\nSystem architecture and Integration\n\nMeeting system requirements while avoiding parasitics and interference is not just a circuit-level challenge. What are the current trends in system architecture and integration? \n\nSystem partitioning\, simulation and integration: Performance / Power / Area \nDigital-analogue interfacing and interconnect. Interference mitigation and isolation \nMulti-die integration: Yield reliability\, Power delivery\, Thermal management \nSignal integrity and noise coupling in advanced packaging\, 2.5D and 3D \nMulti-die mixed signal chiplets and heterogeneous integration \n\n\nApplication drivers for AMS Design\n\nMany emerging technologies are driving AMS innovation. What are the major application challenges pushing the frontier of analogue design today? \n\nFuture compute and AI \nHigh-speed SerDes\, Photonic interconnect\, Clock & data recovery \nPower delivery\, voltage regulation and monitoring \nAnalog and in-memory compute \nIoT\, connectivity\, med-tech and wearables \nLow-noise analogue sensor integration / Energy harvesting \nPhysical AI / Neuromorphic compute \nLow power RF \n\nAGENDA \n\n\n\n\nTIME\nDETAILS\n\n\n\n\n09:15\nRegistration\n\n\n10:00\nTechWorks DESN Introduction – Scene setting & objectives\nJillian Hughes\, Head of Semiconductors\, DESN & Charles Sturman\, CEO\, TechWorks\n\n\n\nThe Future of AMS Design\nHow is AMS design evolving and where are we compared with pure-play digital CMOS\n\n\n10:10\nSystem-First Design for High-Performance Mixed-Signal\nAsad Ali\, Senior IC Architect\, Novamorphic\n\n\n10:30\nBridging the Verification Gap Between Digital and Analog IC Design \nMarcel Ahmedzai\, Application Engineer Architect\, Cadence\n\n\n10:50\nTop‑Down Approach to Mixed‑Signal Verification\nGautham Sathyan\, Mixed Signal Modeling & Verification Engineer\, Cirrus Logic\n\n\n11:10\nVerifying AMS Designs\nMike Bartley\, CEO\, Alpinum\n\n\n11:30\nDiscussion and CTA\n\n\n11:55\nSponsor talk: Lee Harrison\, Director of Product Marketing\, Tessent\, Siemens EDA\n\n\n12:00\nNetworking Lunch\n\n\n\nSystem architecture and Integration\nMeeting system requirements while avoiding parasitics and interference is not just a circuit-level challenge. What are the current trends in system architecture and integration?\n\n\n13:00\nStructured AMS migration: Device-level validation to layout closure with intelligent automation\nChris Yates\, Head of AI and Machine Learning\, Thalia\n\n\n13:20\nRevolutionizing Analog Layout Synthesis through GenAI and Machine Learning Technologies\nNeel Goplan\, Executive Director\, Technical Product Management\n\n\n13:40\nBeyond 1.8 V: Enabling Robust 3.3 V Interfaces in 28 nm CMOS and 7 nm FinFET with Overvoltage Tolerant Specialty I/Os\nBart Keppens\, Chief Business Development\, Sofics\n\n\n14:00\nDiscussion & Call to Action\n\n\n14:25\nBreak\n\n\n\nApplication drivers for AMS Design\nMany emerging technologies are driving AMS innovation. What are the major application challenges pushing the frontier of analogue design today?\n\n\n15:10\nAMS from beamforming arrays to safety critical ASICs\nKonstantinos Glaros\, Associate Director – Analogue IC Design\, Ensilica Plc\n\n\n15:20\nAnalog Scan: A new frontier for Mixed-signal test\nVladimir Zivkovic\, Principal Product Engineer\, Siemens EDA\n\n\n15:40\nDiscussion & Call to Action\n\n\n16:05\nRefreshments and Networking\n\n\n17:00\nClose\n\n\n\n\nAGENDA \n\n\n\n\n09:15\nRegistration\n\n\n10:00\nTechWorks DESN Introduction – Scene setting & objectives\nJillian Hughes\, Head of Semiconductors\, DESN & Charles Sturman\, CEO\, TechWorks\n\n\nThe Future of AMS Design\nHow is AMS design evolving and where are we compared with pure-play digital CMOS\n\n\n10:10\nSystem-First Design for High-Performance Mixed-Signal\nAsad Ali\, Senior IC Architect\, Novamorphic\n\n\n10:30\nBridging the Verification Gap Between Digital and Analog IC Design\nMarcel Ahmedzai\, Application Engineer Architect\, Cadence\n\n\n10:50\nTop‑Down Approach to Mixed‑Signal Verification\nGautham Sathyan\, Mixed Signal Modeling & Verification Engineer\, Cirrus Logic\n\n\n11:10\nVerifying AMS Designs\nMike Bartley\, CEO\, Alpinum\n\n\n11:30\nDiscussion and CTA\n\n\n11:55\nSponsor talk: Lee Harrison\, Director of Product Marketing\, Tessent\, Siemens EDA\n\n\n12:00\nNetworking Lunch\n\n\nSystem architecture and Integration\nMeeting system requirements while avoiding parasitics and interference is not just a circuit-level challenge. What are the current trends in system architecture and integration?\n\n\n13:00\nStructured AMS migration: Device-level validation to layout closure with intelligent automation\nChris Yates\, Head of AI and Machine Learning\, Thalia\n\n\n13:20\nRevolutionizing Analog Layout Synthesis through GenAI and Machine Learning Technologies\nNeel Goplan\, Executive Director\, Technical Product Management\n\n\n13:40\nBeyond 1.8 V: Enabling Robust 3.3 V Interfaces in 28 nm CMOS and 7 nm FinFET with Overvoltage Tolerant Specialty I/Os\nBart Keppens\, Chief Business Development\, Sofics\n\n\n14:00\nDiscussion & Call to Action\n\n\n14:25\nBreak\n\n\nApplication drivers for AMS Design\nMany emerging technologies are driving AMS innovation. What are the major application challenges pushing the frontier of analogue design today?\n\n\n15:00\nAMS from beamforming arrays to safety critical ASICs\nKonstantinos Glaros\, Associate Director – Analogue IC Design\, Ensilica Plc\n\n\n15:20\nAnalog Scan: A new frontier for Mixed-signal test\nVladimir Zivkovic\, Principal Product Engineer\, Siemens EDA\n\n\n15:40\nDiscussion & Call to Action\n\n\n16:05\nRefreshments and Networking\n\n\n17:00\nClose\n\n\n\n\nAMS SpeakersChris Yates\nHead of AI and Machine Learning\, Thalia \nChris Yates\, Vice President of Software Engineering\, leads development of EDA software for analog and mixed-signal design\, optimisation and technology migration. His work applies statistical methods\, mathematical optimisation and AI and machine learning to automate performance tuning and preserve circuit intent across process nodes. With a background in statistics\, mathematics and artificial intelligence\, he focuses on reducing design iteration time while maintaining predictability and robustness in advanced AMS flows. \nPresentation×Structured AMS migration: Device-level validation to layout closure with intelligent automation\nAnalog and mixed signal IP migration using manual or in-house methods is rarely optimal and often slow and difficult. Y et migration remains necessary due to commercial and technical pressures. This session outlines practical ways to make migration predictable and efficient\, including automated device-level comparison\, early PPA assessment and intelligent layout adaptation. Drawing on recent project experience with machine learning-enhanced tools\, it demonstrates how AMS engineers can preserve performance while establishing a repeatable migration methodology. The approach combines traditional analog expertise with selective automation to reduce iteration cycles and improve reliability. The discussion will show where intelligent tools can augment\, not replace\, engineering judgment in critical design decisions. \nCloseMarcel Ahmedzai\nApplication Engineer Architect\, Cadence \nMarcel Ahmedzai is an engineering architect at Cadence with a focus on mixed signal verification and is based in Bracknell\, England. Prior to Cadence he was a CAD engineer at Mitel Semiconductor and Zarlink Semiconductor. Marcel has been with Cadence for over 20 years and has a bachelor’s degree in Mathematics from the University of Hertfordshire. \nPresentation×Bridging the Verification Gap Between Digital and Analog IC Design\nAs transistor geometries continue to shrink\, modern integrated circuit designs face escalating complexity that challenges the effectiveness and efficiency of traditional verification practices. Even at the block level\, the functional checks required to ensure correct behavior demand substantial time and resources\, and this burden increases dramatically when scaling to chip‑level and system‑level verification. In digital design\, these challenges have long been addressed through established verification methodologies\, dedicated verification engineers\, and standardized frameworks such as UVM. In contrast\, analog and mixed‑signal (AMS) design teams often lack a comparable verification mindset\, leading to late discovery of bugs\, costly respins\, and delays in time‑to‑market. This paper outlines the requirements and methodologies needed to elevate AMS verification to the maturity of its digital counterpart. By examining current gaps\, resource impacts\, and emerging best practices\, we provide a structured view of how systematic AMS verification can significantly reduce design risk and improve overall product quality. \nCloseMike Bartley\nF0under and CEO\, Alpinum \nMike started in software testing in 1988 after completing a PhD in Math\, moving to semiconductor Design Verification (DV) in 1994\, verifying designs (on Silicon and FPGA) going into commercial and safety-related sectors such as mobile phones\, automotive\, comms\, cloud/data servers\, and Artificial Intelligence. Mike built and managed state-of-the-art DV teams inside several companies\, specialising in CPU verification. \nMike founded and grew a DV services company to 450+ engineers globally\, successfully delivering services and solutions to over 50+ clients . The company was acquired by Tessolve Semiconductors in 2020 and Mike worked at Tessolve as SVP. \nMike started Alpinum in April 2025 to deliver a range of start-of-the art industry solutions. \nPresentation×Verifying AMS Designs\nWe will be investigating strategies for verifying AMS designs from test planning\, through test bench design and bring up\, to test generation\, closure and signoff. The talk will focus on practical\, best-practice verification solutions for a variety of designs\, so that the delegates can take away ideas that they can start using immediately. \nCloseAsad Ali\nSenior IC Architect ‑ Analogue and Mixed Signal\, Novomorphic \nAsad Ali\, Senior IC Architect at Novomorphic\, champions a System First approach to analogue and mixed-signal development. He has held leadership roles at Maxim Integrated\, OnSemi\, Dialog Semiconductor and LSI Logic\, leading the development of high-volume RFIC\, power and mixed-signal IC products from concept to production. \nPresentation×System-First Design for High-Performance Mixed-Signal\nIn modern mixed-signal systems\, the analog figure-of-merit (FOM)\, capturing the signal-to-noise ratio (SNR) delivered per unit power over a defined bandwidth\, is a key determinant of overall system efficiency. As CMOS technology continues to scale\, reduced intrinsic gain\, lower supply voltages\, and increased variability are fundamentally limiting the ability of traditional analog design techniques to sustain competitive FOM\, directly impacting power budgets\, performance headroom\, and implementation cost. \nThis talk reframes the problem from a circuit-centric challenge to a system-level opportunity – a System First Approach. Rather than relying solely on device-level optimisation\, we examine architectural and system-partitioning strategies that shift performance dependencies. \nWe present practical\, system-driven design methodologies that mitigate technology-imposed analog limitations\, enabling next-generation mixed-signal platforms to achieve aggressive performance targets while improving power efficiency\, scalability\, and time-to-market in line with Power-Performance-Cost objectives. \nCloseKostas Glaros\nAssociate Director – Analogue IC Design\, Ensilica Plc \nKostas Glaros is an analogue/mixed-signal technical lead with EnSilica Plc. Over the past decade he has led teams bringing multiple mixed-signal ASICs from initial concept to mass production. He focuses on medical\, automotive\, and industrial control applications\, and has a keen interest on design methodology and tools. Kostas holds a PhD in low-power medical electronics from Imperial College London. \nPresentation×AMS from beamforming arrays to safety critical ASICs\nIn large\, multi-channel SoCs\, AMS verification is essential for validating the integration of multiple analogue channels operating concurrently alongside complex digital signal processing. Safety-critical ASICs\, such as industrial and automotive controllers\, demand demonstrable vertical integration and traceable compliance with requirements. This talk discusses examples of AMS and DMS verification in such applications and some associated challenges. \nCloseGautham Sathyan\nMixed Signal Modeling & Verification Engineer\, Cirrus Logic \nGautham Sathyan is part of the Mixed-Signal Modeling and Verification group at Cirrus Logic in the Newbury office. His work spans a wide range of responsibilities\, including early stage architectural modeling of mixed signal blocks\, requirements definition\, and establishing analog/digital boundary and the chip level schematic hierarchy. He is involved in netlisting and chip bring up DMS simulation\, SystemVerilog real number modeling of low level analog cells\, and to define and implement chip level AMS simulations. \nWith a background in analog design\, Gautham particularly enjoys the challenges of modeling and debugging complex mixed signal systems. Outside of work\, he spends most of his time running after his young children\, though he hopes to one day start learning to play Indian music on the guitar. \n×Top‑Down Approach to Mixed‑Signal Verification\nA framework for first‑silicon success \nSilicon Respins and late surprises can feel inevitable on complex mixed‑signal ASICs\, especially when sophisticated digital control meets rich analog content. They needn’t be\, argues Gautham Sathyan\, in this fast‑paced\, practitioner‑focused talk as he lays out a concrete framework combining a top‑down\, model‑driven verification methodology with tight cross‑team alignment and disciplined use of AMS co‑simulation. 3 key CTAs from this talk : \n\nModel early\, verify continuously.\nCo‑sim sparingly\, where it counts.\nShip together\, not in silos.\n\nClosePresentationVladimir Zivkovic\nPrincipal Product Engineer\, Siemens EDA \nVladimir Zivkovic is a principal product engineer for Analog Mixed-Signal and Defect-oriented Test at Siemens EDA. He graduated from the Faculty of Electrical Engineering at the University of Nis in Former Yugoslavia and obtained PhD in Electrical Engineering from the University of Twente\, the Netherlands. \nHe has more than 20 years of industrial experience in Mixed-signal DfT\, test flow automation\, test coverage analysis and AMS verification. His previous affiliations include Philips Research (Netherlands)\, NXP Semiconductors (Netherlands)\, D4T Systems (small startup company\, Netherlands)\, Nikhef/CERN (Netherlands/Switzerland)\, Cadence Design Systems (Scotland\, UK) and Infineon (Denmark). He is program committee member of IEEE European Test Symposium (ETS) and provided significant contribution during the development of IEEE 2427 standard for Analog Defect Modeling and Coverage. He is also vice chair of IEEE P1687.2 (Analog Test Access standardization) working group. \nPresentation×Analog Scan: A new frontier for Mixed-signal test\nDeveloping tests for designs with mixed-signal circuits has always been a bottleneck during IC product sign-off\, regardless of the application. This talk presents a revolutionary approach for creating efficient manufacturing mixed-signal tests that reduce test costs and test escapes. The methodology is called analog scan and requires DfT of a circuit-under-test (CUT) to inject stimulus signals and observe responses. The inserted circuitry is not placed in series with signal propagation paths\, and it is turned off in the mission mode. The control and output of the DfT circuitry is connected to test data registers (TDRs)\, typically placed outside the mixed-signal block under test. \nAnalog scan methodology brings multiple benefits. First\, there is a massive decrease of test cost\, since analog scan tests run orders of magnitude faster than a large majority of spec-based tests on ATE. Analog defect simulation also runs much faster than for spec-based tests. With appropriate automation\, top-level test development is also significantly accelerated. Defect coverage figures achieved with analog scan are usually higher than those obtained with functional tests. Lastly\, analog scan facilitates diagnosis of field returns. \nBart Keppens\nChief Business Development\, Sofics \nBart Keppens received an engineering degree in electronics in 1996 and started his career at imec in Belgium. From 2002 he joined Sarnoff Europe\, solving on-chip ESD related problems for customers worldwide. After a management buy-out in June 2009\, Sarnoff Europe became ‘SOFICS – Solutions for ICs’ where Bart is responsible for global business development. Bart (co-) authored more than 40 peer-reviewed published articles on ESD protection. \nPresentation×Beyond 1.8 V: Enabling Robust 3.3 V Interfaces in 28 nm CMOS and 7 nm FinFET with Overvoltage Tolerant Specialty I/Os\nAs CMOS nodes scale\, designers face a widening gap between core capabilities and system-level requirements. While foundry GPIOs in FinFET and GAA processes typically top out at 1.8V\, many applications still demand 3.3V “Over-Voltage Tolerant” (OVT) interfaces for legacy compatibility and robust system integration. Conversely\, the rise of chiplet architectures introduces the opposite challenge: Die-to-Die (D2D) interfaces that must operate at specialty voltages below the typical GPIO range (1V or lower) to minimize power and maximize speed. \nThis presentation explores the design and ESD protection of these specialty interfaces. We examine the “3.3V in a 1.8V process” dilemma\, focusing on stacking techniques to maintain Safe Operating Area (SOA) during power sequencing and transient events. We then pivot to the unique requirements of chiplet interconnects. Unlike standard I/Os\, D2D interfaces require: (a) Specialized ESD: Traditional >2kV HBM protection is often overkill for D2D\, introducing excessive parasitic capacitance that limits bandwidth. (b) Thin-Oxide Integration: To achieve high speeds\, D2D circuits utilize sensitive thin-oxide transistors that are easily damaged without custom ESD clamps. (c) Area Efficiency: With thousands of required connections\, standard I/O pads consume prohibitive silicon area. \nAttendees will gain a practical framework for specifying and verifying both higher and lower voltage specialty I/Os\, with an emphasis on co-designing circuits and ESD to optimize PPA in modern\, heterogeneous systems. \nLee Harrison\nDirector of Product Marketing\, Tessent\, Siemens EDA \nLee Harrison is Director\, Product Marketing\, with Siemens Tessent Division. He has over 25 years of industry experience working with Siemens Tessent DFT products\, with a focus on safety and security. Lee Received his BEng in MicroElectronic Engineering from Brunel University London in 1996. Lee presents regularly at industry conferences such as DAC\, ITC\, VTS\, ETS\, and DATE. \nNeel Goplan\nExecutive Director\, Technical Product Management\, Synopsys \nNeel Gopalan is an Executive Director\, in the Products and Market group. Neel leads Technical Product Management for AMS tools including Custom Compiler\, PrimeSim and Characterization. Neel has been with Synopsys for the last 20 years; during this time he has been part of Custom Compiler Product Engineering team. He was an integral part of the team that built Custom Compiler along with all the collaterals needed for Custom Design. Neel and his team built industry’s 1st iPDK\, which is now the standard for PDKs in the industry. Neel now leads Analog Design Migration\, ASO and Layout Synthesis. Prior to Synopsys\, Neel worked for Cadence for 5 years \nPresentation×Revolutionizing Analog Layout Synthesis through GenAI and Machine Learning Technologies\nThe rapid advancement of semiconductor technology necessitates innovative approaches to Analog Layout Synthesis\, a critical aspect in circuit design for FinFET and GAA nodes. This presentation introduces Industry’s First transformative potential of Generative AI (GenAI) and Machine Learning (ML) in automating and optimizing the analog layout process. We will discuss how GenAI can generate high-quality layout designs by learning from vast datasets of existing designs\, while ML algorithms enhance the efficiency of design creation and predictions. Furthermore\, we will delve into the role of AI in facilitating intelligent decision-making throughout the design process\, enabling adaptive responses to design constraints and objectives. By integrating these cutting-edge technologies\, we aim to significantly reduce design time\, improve layout quality\, and foster innovation in analog circuit design. This presentation will provide insights into the methodologies employed\, the challenges encountered\, and the future directions of analog layout synthesis in the context of AI-driven advancements \n×Meet the Students\n\nFrom RTL and verification to open-source silicon tapeouts\, these exceptional students are already making an impact in digital chip design \n James Ashie Kotey | Electronics & Computer Engineering\, University of Sheffield | IC Engineering Intern at EnSilica \nJames has contributed to commercial ASIC projects in RTL design and functional verification\, and has led three open-source silicon projects from concept to tapeout using open-source EDA tools and PDKs. \nCarys MacIntyre | Robotics Engineering (Integrated Master’s)\, University of Bath | Hardware Intern at Siemens EDA (Tessent Embedded Analytics) \nCurrently on a 12-month placement in digital RTL verification\, Carys is gaining hands-on verification experience alongside her master’s studies. \nCharlie Teare | Mechatronics & Robotic Systems (BEng with Year in Industry) \, University of Liverpool \nFollowing a placement with EnSilica’s digital design team\, Charlie continues collaborating with industry while completing his final year project focused on a fabric/interconnect generator. \nRonit Ravi | Electronic Engineering\, Imperial College London \nNow in his final year\, Ronit previously completed a placement in Design Verification at Siemens EDA and continues to collaborate during his master’s research. \nThis event provides students and early-career designers with direct exposure to professionals in digital chip design \,  embedding their learning and offering tangible inspiration for careers in the UK semiconductor sector. \n\nDigital Design Early Careers SpeakersHaydn Povey\nFounder and CEO\, SCI Semiconductor \nWith over 30 years experience in the technology domain Haydn has unparalleled experience in microprocessor IP\, cyber security\, and real world cyber-physical systems. \nHaving led the introduction of Arm Cortex-M processors he subsequently led the Processor Divisions security technologies\, including TrustZone & SecurCore. \nHe is a founder board member of the IoT Security Foundation. \nDave Sanders\nAssociate Fellow\, Rolls-Royce \nDave Sanders is an Associate Fellow at Rolls-Royce specialising in the development of complex electronic hardware. He has 28 years of experience working in the electronics industry\, with 26 of those developing the safety critical microprocessors that form the heart of the Rolls-Royce control systems for both aerospace and non-aerospace applications. \nDave is a member of the European DO254 Users Group since 2012 and has contributed to various regulation working groups including co-authoring AMC 20-152A. He became a Fellow of the IET in 2018 and was awarded the Rolls-Royce Controls Gold Innovation Award in 2015 in recognition of the successful development of the sixth-generation safety critical microprocessor\, which has already accumulated over 30 million fault free flying hours. \nIn his spare time\, Dave is a keen runner and currently Lichfield Running Club Secretary. \nMichael O’Sullivan\nEngineering director\, Cadence \nMichael O’Sullivan is an engineering director at Cadence with a focus on verification and is based in Edinburgh\, Scotland. Michael has been with Cadence for over 27 years with various roles in sales\, marketing and design services. \nPrior to Cadence he was a design engineer at S3 Group in Dublin\, Ireland and at Philips in Eindhoven\, The Netherlands. Michael has an Masters of Engineering Science from the National University of Ireland. \nLoay Qteet\nStaff Application Engineer\, Synopsys \nLoay Qteet\, Applications Engineering\, Staff Engineer at Synopsys\, with six years of experience in the Electronic Design Automation (EDA) field. He specializes in physical design\, RTLIIGDS flow development\, and EDA applications of Implementation and AI. Loay has played a key role in supporting various customer\, helping them to achieve their goals effectively and ensuring that Synopsys products meet their evolving requirements. \nCatriona Wright\nCo-founder\, Chipletti \nCatriona Wright is co-founder of Chipletti\, a Cambridge-based fabless semiconductor startup developing AI accelerators for physical AI systems that require low power\, high performance real-time operation within tight SWaP-C constraints. She works across strategy\, partnerships\, and operations while helping translate emerging AI compute needs into practical hardware solutions. \nRead More \nCatriona has more than 25 years of experience delivering complex semiconductor products from concept through to production. Her career spans digital design\, program leadership\, and scaling multidisciplinary teams to deliver advanced silicon. Before founding Chipletti\, she held roles at both start-ups and large companies including Riverlane\, DisplayLink\, Cambridge Semiconductor\, TTPCom and Nortel Networks\, leading IC development programmes and coordinating cross-functional engineering teams. \nShe holds a First Class MEng in Electrical and Electronic Engineering from the University of Edinburgh and an MBA from The Open University. Catriona is passionate about building strong deep tech teams and helping grow the semiconductor ecosystem in the UK. She is also active in outreach\, running coding clubs for primary school students and encouraging more young people – particularly girls – to explore engineering. \n\n\nModerator \n\nMatt Cossins\nEcosystem Development Manager\, Arm \nMatt Cossins is an Ecosystem Development Manager in Arm’s AI and Developer Platforms group\, where he supports the adoption of Arm-powered AI compute platforms through developer education\, enablement\, and collaboration between industry and academia. \nRead More \nAn alumnus of the UKESF programme\, he holds an MEng in Electrical and Electronic Engineering from the University of Nottingham\, where his thesis focused on neuromorphic AI. He previously held engineering roles at Capgemini\, delivering software and embedded research projects for multiple clients\, and at Cambridge-based cellXica\, where he worked on embedded and RTL design for software-defined radio in 5G communications. \nMatt is a recipient of awards from organisations including the IET\, UKESF\, and Electronics Weekly\, and mentors engineering students through the Arkwright Scholarships Trust. \n\nRaj Gawera\nChief Operating Officer\, UK Semiconductor Centre \nRaj has over 30 years of experience in the semiconductor field having held senior technical and commercial roles in semiconductor organisations spanning IP\, Fabless and IDM business models. He is now COO of the newly formed UK Semiconductor Centre – with an ambitious plan to strengthen the UK semiconductor ecosystem and grow international partnerships. \nRead More \nIn his early career\, Raj was part of initial IEEE 802.11 team to define first WLAN standard in 1996 – a technology which has now shipped many billions of units. Raj also helped pioneer the first 3G data transmissions working with Motorola and others to demonstrate one of the first 3G video calls at the 3GSM show in 1998 – many years before 3G licences were awarded. \nRaj was a founder member of 3G technology startup UbiNetics (1999)\, that successfully exited in 2005 for over $120m USD. As part of that deal\, Raj joined CSR and ultimately took the role of VP Marketing where he was part of the team that acquired SiRF Technologies for $136m (2009) to add GPS technology to CSR portfolio. In 2012\, he helped sell CSR’s handset business to Samsung in a deal worth $310m for 310 staff. As part of Samsung\, Raj was promoted to VP heading up the SCSC division leading the silicon and software development for Samsung’s chipsets for over a decade\, providing connectivity technology that shipped in hundreds of millions of Samsung products. \nRaj has held a number of board positions including Chair of Cambridge Wireless and NED for CSA Catapult bringing experience and advice on the global semiconductor market. \n\nMahdieh Ghoddusi\nDirector of Delivery\, UKESF \nMahdieh Ghoddusi\nDirector of Delivery\, UKESF \nProf. Nick McKeown
URL:https://desn.org.uk/event/designing-the-future-analogue-mixed-signal-ams/
LOCATION:Regents University London\, Inner Circle\, Regent’s Park\, London\, NW1 4NS
CATEGORIES:DESN Event
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BEGIN:VEVENT
DTSTART;TZID=Europe/London:20260416T100000
DTEND;TZID=Europe/London:20260416T143000
DTSTAMP:20260413T174628Z
CREATED:20260116T151918Z
LAST-MODIFIED:20260413T174628Z
UID:23196-1776333600-1776349800@desn.org.uk
SUMMARY:FPGA Frontrunners Event
DESCRIPTION:FPGA Frontrunner EventREGISTERCLICK HERE to find out more about the FPGA FrontrunnersField Programmable Gate Arrays (FPGAs) play a critical role in modern electronic systems\, powering applications that range from everyday consumer products to mission-critical infrastructure. Their ability to be customized and reconfigured after deployment makes them uniquely valuable in fast-moving technology environments. At the same time\, this adaptability introduces distinct security challenges that must be carefully addressed. \nBecause FPGAs can be reprogrammed in the field\, they present a broader attack surface than fixed-function hardware. Threats targeting configuration data\, intellectual property\, firmware integrity\, and runtime behavior can compromise not only the device itself\, but also the larger systems that rely on it. As FPGAs are increasingly used to support advanced workloads—including data-intensive and intelligent processing—security risks continue to grow in both scope and impact. \nEffective FPGA security extends beyond physical protection. It encompasses the full lifecycle and ecosystem surrounding the device\, including design tools\, bitstreams\, firmware\, software interfaces\, and data flows. In systems that incorporate adaptive or AI-assisted functionality\, ensuring trust\, integrity\, and resilience across this ecosystem is especially critical. \nThis event explores the evolving landscape of FPGA security\, highlighting emerging threats\, recent advances\, and proven mitigation strategies. Through expert insights and real-world case studies\, the program aims to equip engineers\, researchers\, and security professionals with practical guidance for securing FPGA-based systems today and in \nknowledge\, techniques\, and assurance frameworks necessary to design systems that are not only resilient and secure—but demonstrably so. \nWho Should Attend\nFPGA Designers and EngineersSystem ArchitectsSafety and Security SpecialistsSupply Chain ProfessionalsIndustry Regulators and Standards Bodies \nWhy Attend? \n\nGain insights from leading experts on the evolving risks and mitigation strategies\nLearn how to meet functional safety and security requirements across multiple industries\nNetwork with industry peers and potential collaborators\nParticipate in discussions on best practices\, regulatory trends\, and real-world case studies\n\nOutline Agenda\n\n\n\n\nTime\nDetails\n\n\n\n\n10:00\nRegistration\n\n\n10:30\nMicrochip Secure FPGA’sIan PearsonPr. ESE\, Microchip\n\n\n11:00\nA Visual Demonstration of True Random Numbers from a Quantum ComputerPhill J PaynePrincipal Digital Design Engineer\, Novomorphic\n\n\n11:30\nAre FPGAs unique for security?Martin ThompsonSenior Technical Specialist\, ZF Engineering Solutions\n\n\n12:00\nBeyond Bitstream Encryption: FPGA Security for High-Assurance SystemsDaniel TeeSenior Firmware (FPGA) Engineer\, Leonardo\n\n\n12:30\nNetworking Lunch\n\n\n13:30\nOverview of prEN50767 : CRA Vertical Standard for FPGA/ASICPeter TrottStaff FAE\, Microchip\n\n\n14:00\nHardware-Rooted Bitstream SecurityMans AhmadianChief Innovation Officer\, Sundance\n\n\n14:30\nWrap Up\n\n\n14:45\nClose\n\n\n\n\nPhill J Payne\, Principal Digital Design Engineer\, Novomorphic\nPresentation: A Visual Demonstration of True Random Numbers from a Quantum Computer \nTrue randomness is one of those things everyone assumes they have… right up until security\, trust\, or assurance actually matters.\nThis session reveals a practical way to pull physical entropy from a real quantum computer and inject it into FPGA and embedded systems as a usable\, engineering-grade input. You’ll see quantum behaviour turned into something tangible and immediate — a live “quantum dice” demonstrator that makes the invisible visible — and you’ll learn why this matters far beyond novelty. \nWe’ll explore what changes when your randomness isn’t “noisy enough” pseudo-random\, but rooted in genuine physical uncertainty\, and how that can reshape thinking around key generation\, nonces\, reseeding\, and trusted system design. A live comparison between simulation and real quantum hardware draws a clear line between “looks random” and “is random”. \nIf you build secure edge systems and care about trust boundaries\, this will change how you think about entropy. \nprofile×Phill J Payne\nPhill J Payne is Principal Digital Design Engineer at Novomorphic\, specialising in secure\, real-time FPGA and embedded architectures for edge AI. He is developing convolution acceleration and a modular hardware fabric that composes reconfigurable pipelines\, reduces memory pressure\, and delivers high-performance vision and inference at the edge. Across 26 years\, Phill has turned novel architectural ideas into deployable systems under tight power\, latency\, throughput\, and reliability constraints\, with deep experience in security-grade FPGA development and signal-processing workloads. Previously\, he delivered end-to-end FPGA firmware and software for advanced systems\, including a patented communications technique designed to operate in contested jamming environments\, later acquired by a major defence prime. He also built specialised training systems used in preparation for the London 2012 Olympic Games\, translating complex engineering into practical tools. \nMartin Thompson\, Senior Technical Specialist\,  ZF Engineering Solutions\nPresentation: Are FPGAs unique for security?\n \nIn this talk we will investigate the degree to which systems containing programmable logic (including FPGAs) can be considered “unique” in their security requirements and implementation options\, when compared to more conventional microcontroller and desktop processor systems. \nWe will briefly define what we mean by “security” in this context (both in terms of market requirements and attacker motivations) and what primitives can be used to achieve it. A review of the variety of potential attacks will be presented and we will spend some time on the peculiarities of FPGA-based systems by comparing them directly with other implementation strategies. Finally\, we will conclude with an answer to the question posed in the title. \nprofile×Martin Thompson\nMartin Thompson is a Senior Technical Specialist at ZF Engineering Solutions. He has spent over 30 years developing systems and algorithms for products in the automotive and aerospace domains. He enjoys working across the full range of software and electronics disciplines\, from desktop algorithm development to microcontroller\, DSP and FPGA code as well as electronic design\, PCB layout (and when the need arises\, soldering!). He specialises in optimisations of whole electronic systems\, based on a detailed understanding of the trade-offs across multiple domains. Particular highlights have included the development of very low-cost FPGA-based imaging and radar-systems. \nSince 2015\, Martin has been heavily involved in the cybersecurity of embedded systems and is currently the technical leader of an penetration-testing team with an embedded-system focus. He contributes to the Internet of Things Security Foundation Assurance Framework\, the Automotive Threat Matrix\, and is a member of the MITRE hardware CWE SIG and the CWE-RTL working group. Finally\, he spends some of his time researching novel side-channel attacks in pursuit of a PhD\, with the University of Durham. \nMans Ahmadian\, Chief Innovation Officer\, Sundance\n\nPresentation: Hardware-Rooted Bitstream Security and Secure Manufacturing Workflow\n \nA Defense-Grade Implementation Using PolarFire FPGA on Sundance PCIe104N Platform As FPGAs become central to mission-critical defense and aerospace systems\, the security challenge has shifted. It is no longer enough to protect configuration data in the fi eld; we must also secure it during manufacturing\, programming\, testing\, and across the entire supply chain. When production is distributed across multiple facilities and third-party partners\, the FPGA bitstream becomes a high-value target\, vulnerable to interception\, overbuilding\, hardware substitution\, or reverse engineering. This talk presents a defence-grade secure provisioning workflow implemented on the Sundance PCIe104N platform\, built around the PolarFire MPF500T FPGA\, and explains how it establishes trust from silicon to system deployment. \nRead More \nAt the heart of this approach is hardware-rooted security. PolarFire devices generate a unique\, silicon-derived identity using Physically Unclonable Functions (PUFs)\, meaning that no two FPGAs are electrically identical and no identity can be copied or cloned. During secure provisioning\, this identity is validated before any sensitive key material is transferred. The customer’s encrypted bitstream and User Encryption Key are generated inside their own trusted environment and securely delivered for programming using Microchip’s Secure Production Programming Solution. If authentication fails at any stage\, such as in a dummy FPGA impersonation attempt\, the process stops immediately. No keys are exposed\, and no firmware is released. What this workflow ultimately provides is confidence. Confidence that the hardware being programmed is genuine. Confidence that only the approved number of boards can ever be provisioned. Confidence that the bitstream cannot be intercepted\, modified\, or extracted through side-channel attacks. By combining controlled manufacturing\, independent validation\, hardware security modules\, authenticated encryption\, and built-in DPA countermeasures\, Sundance ensures customers receive fully tested\, securely programmed boards\, without any risk of supply-chain compromise or intellectual property leakage. Today\, I will walk you through how this architecture works and why it sets a scalable model for secure FPGA manufacturing. \n\nprofile×Mans Ahmadian\nMans Ahmadian serves as the Chief Innovation Officer at Sundance\, where he leads the architecture of next-generation\, high-density AI Systems-on-Modules (SoMs). In this role\, he directs the design of specialized AI Engines and systems otimized for low-power\, high-throughput inference in rugged environments. He is instrumental in bridging the gap between AI frameworks and SundanceDSP hardware. Additionally\, his work ensures the reliability of autonomous Edge AI platforms in mission-critical settings by optimizing SWaP (Size\, Weight\, and Power) solutions and integrating safety-critical\, “fail-safe” R&D workflows. \nThroughout his career\, he has been granted numerous patents for his innovations in image processing\, advanced camera systems and imaging sensor operations. His technical and commercial achievements have earned him several prestigious honors\, including the IET (Institute of Engineering and Technology) Innovation Award in software development\, the SMART::SCOTLAND Innovation Award\, and a Business Plan Competition win. These accolades are supported by a robust academic foundation\, including a PhD in Medical Image Processing\, an MSc in Biomedical/Medical Engineering\, and a BSc in Electronics from The University of Edinburgh\, and postgraduate certificates in Health Data Science and Big Data and AI. \nDaniel Tee\, Senior Firmware (FPGA) Engineer\, Leonardo\n\nPresentation: Beyond Bitstream Encryption: FPGA Security for High-Assurance Systems\n \nField programmable gate arrays (FPGAs) are increasingly deployed in systems where failure or compromise is not an option – from defence and aerospace to critical infrastructure and advanced industrial platforms. In these high assurance environments\, security requirements extend beyond the protections normally offered by device vendors. Engineers must consider the broader context of threats\, deployment conditions\, and system level risk. \nRead More \nThis presentation explores the evolving landscape of FPGA security and outlines practical considerations for designing and deploying secure programmable logic systems. It introduces the principles that shape high assurance engineering\, highlights common security challenges unique to reconfigurable hardware\, and discusses methods for establishing trust from initial configuration through runtime operation. The talk also touches on modern approaches to isolation\, secure execution\, and configuration protection\, alongside emerging trends that FPGA developers should be aware of as threats and technologies continue to advance. \nAttendees will gain a clearer understanding of how to think about security in FPGA based systems\, along with a set of concepts and design patterns that can be adapted to a wide range of high assurance applications. \n\nprofile×Daniel Tee\nDaniel Tee is a Senior Firmware (FPGA) Engineer at Leonardo\, working within the product security team. He joined Leonardo as a graduate in 2022 after completing an integrated MEng in Electronics and Computer Science at the University of Edinburgh\, where he focused on a number of cybersecurity modules in his final year. Daniel now applies his interest in hardware security to developing robust FPGA‑based security solutions for customer‑driven\, mission‑critical applications. \nIan Pearson\, Pr. ESE\, Microchip Technology Inc.\n\nPresentation: Leveraging Microchip Secure FPGAs\n \nThe foundation of a secure end product lies in the right choice of components. CRA requires a ‘Secure by Design’ approach to product development and support throughout the lifecycle. Microchip FPGA’s have a long history of secure FPGA’s designed to meet the most demanding of military applications but available to all \nprofile×Ian Pearson\nIan Pearson is a Principle Embedded Solutions Engineer with Microchip Technology covering FPGA\, Security and IoT. He is also the chair of the IoT Security Foundation – Security Assurance Framework Working Group. \nPeter Trott\, Staff FAE\, Microchip Technology Inc.\n\nPresentation: Overview of prEN50767 : CRA Vertical Standard for FPGA/ASIC\n \nThe EU CRA requirements can be met via a presumption of conformity using horizontal and vertical harmonised standards. These standards are in development and will release very close to the enforcement date. In this session we will give some insight into what is coming in the vertical standard for FPGA/ASIC. The prEN50767 standard provides the requirements for FPGA/ASIC vendors to meet the Important Class I categorisation of FPGA/ASIC in the EU CRA. \nprofile×Peter Trott\nPeter Trott is a Staff Applications engineer at Microchip with over 30yrs experience in the FPGA sector. He has extensive experience in both military and industrial design using FPGA’s. Peter is also a key member of the EU TC47x WG4 Trusted Silicon work group for FPGA/ASIC who are creating the prEN50767 harmonised standard relative to the Important Class I FPGA/ASIC with security features
URL:https://desn.org.uk/event/fpga-frontrunner-2026/
LOCATION:Microchip\, 720 Wharfedale Road\, Winnersh\, RG41 5TP
CATEGORIES:DESN Event
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BEGIN:VEVENT
DTSTART;VALUE=DATE:20260614
DTEND;VALUE=DATE:20260618
DTSTAMP:20260428T171041Z
CREATED:20260428T170947Z
LAST-MODIFIED:20260428T171041Z
UID:23586-1781395200-1781740799@desn.org.uk
SUMMARY:29th World Micromachining Summit
DESCRIPTION:
URL:https://mms2026.soton.ac.uk/#new_tab
LOCATION:Southampton
CATEGORIES:DESN Promoted Event
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DTSTART;TZID=Europe/London:20260617T091500
DTEND;TZID=Europe/London:20260617T172000
DTSTAMP:20260428T171515Z
CREATED:20260224T120629Z
LAST-MODIFIED:20260428T171515Z
UID:23346-1781687700-1781716800@desn.org.uk
SUMMARY:Women in TechWorks: Engineering Intelligently
DESCRIPTION:Women in TechWorks Launch EventRegisterConnecting Talent\nWomen in TechWorks comes together in person for the first time — bringing the community to the heart of the UK’s technology ecosystem. \nHosted at Arm\, this landmark event builds on the program created through tech talks\, town halls and fireside chats. \nWhy Attend?\nTechWorks sits at the centre of the UK’s leading technology communities — semiconductors\, embedded systems\, cybersecurity\, future compute and AI. \nOn 17 June\, we bring together the full spectrum of talent across these sectors for a day of: \n\nInspiring talks from exceptional women in industry\nPanel discussions spanning leadership\, innovation and visibility\nNetworking across career stages — from early careers to founders and C-suite leaders\n\nWho It’s For\nThis event is open to everyone. \nWhile it showcases outstanding women shaping UK technology\, it’s designed for everyone \, and be part of a stronger\, more inclusive tech ecosystem. \nFrom Momentum to Action\nWomen in TechWorks is focused on: \n\nLeadership\nMentorship\nVisibility\n\nThis first face-to-face event brings those pillars to life \nJoin us for a day that connects people\, ideas and opportunity.
URL:https://techworks.org.uk/event/women-in-techworks-engineering-intelligently/#new_tab
LOCATION:Arm\, Cambridge\, CB1 9NJ
CATEGORIES:TechWorks Event
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BEGIN:VEVENT
DTSTART;VALUE=DATE:20260623
DTEND;VALUE=DATE:20260624
DTSTAMP:20260511T083050Z
CREATED:20260414T123406Z
LAST-MODIFIED:20260511T083050Z
UID:23540-1782172800-1782259199@desn.org.uk
SUMMARY:Verification & Semiconductors Futures Conference UK 2026
DESCRIPTION:Verification Futures UK 2026\, co-located with Semiconductors Futures 2026 co-organised by Tessolve and Alpinum.\nThe conference continues its strong tradition of delivering a unique blend of conference presentations\, exhibitions\, training\, and industry networking sessions focused on the challenges faced in hardware and software verification. The event remains an important forum for end-users to define their verification challenges and collaborate with engineers\, researchers\, and vendors to shape practical solutions. In 2026\, Verification Futures continues to strengthen its core emphasis on verification methodologies\, DV tools\, and engineering workflows\, including areas such as formal methods for complex SoCs\, CPU & RISC-V verification\, open-source and licence-free verification tools\, AI in design verification (AI in DV)\, verification planning and coverage\, and HW/SW co-verification. \nSemiconductors Futures 2026 brings together the semiconductor community\, covering AI/ML in IP & SoC design\, AI’s impact on EDA and workflows\, FPGA & mixed-signal\, with a focus on the automotive\, data centre\, and AI products. New tracks consider emerging technologies such as quantum computing\, photonics\, and chiplets\, as well as startups and investments. We expect 50+ engineering students to attend a separate session. \nDetailsSimon Southwell\nSystems Consultant\nWyvern Semiconductors \n×Simon Southwell\nComplex protocol modelling with OSVVM co-simulation\, exploring the PCIe VC \nA look at OSVVM co-simulation features and their use for constructing complex protocol verification component using PCIe as an example. It looks at the integration of the PCIe GEN1/GEN2 C model from the presenter’s pcieVHost project\, using OSVVM’s co-simulation capabilities\, to construct an OSVVM compatible Verification Component (VC)\, used like any other VHDL based VC\, but with additional features\, to drive 3rd party PCIe IP. An example of driving Altera’s Cyclone V Hard IP for PCI Express is discussed. \nBiography \nEngineer with 35+ years in R&D\, with experience in ASIC design\, FPGA\, and embedded software development. Currently working on developing open-source IP in areas such as co-simulation and system modelling. A collaborator on the OSVVM project\, adding and supporting its co-simulation capabilities and developing verification IP. \nAreas of experiences include logic IP for both ASIC and FPGA\, logic verification\, HPC\, processor systems\, networking (802.3 and proprietary)\, embedded software\, co-simulation technology\, software modelling of SoC systems\, data compression logic\, PCIe endpoint design\, cellular (3G and 4G)\, wireless (802.11 and 802.15.4). Joint or sole author on several logic IP related patents. \nDetailsRojalin Mishra\nLead Verification Engineer\nRiver Lane \n×Rojalin Mishra\nFrom Qubits to Confidence: Verifying Quantum Error Correction \nQuantum error correction (QEC) introduces fundamentally new challenges for verification\, where probabilistic behaviour and correlated errors break many conventional methodologies. This talk explores how we adapt verification strategies to this domain\, including designing testbenches for probabilistic measurement data\, modelling spatially and temporally correlated noise\, and defining meaningful coverage for error correction circuits. \nThrough real debugging case studies\, we highlight subtle failure modes unique to quantum systems—such as silent corruption during syndrome extraction—and discuss approaches to validating decoder behaviour across complex syndrome spaces. We also examine how verification can be performed under realistic noise distributions to build confidence in system-level reliability. \nBio: I am an Electronics and Communications engineer with over a decade of experience in ASIC/FPGA verification\, specialising in complex digital systems and verification methodologies. I currently serve as a Lead Verification Engineer\, driving UVM-based verification for Quantum Error Correction within the rapidly evolving field of Quantum Computing. \nDetailsSteinn Gustafsson\nFounder\nChevin Technology \n×Steinn Gustafsson\nPresentation Title: Complex protocol modelling with OSVVM co-simulation\, exploring the PCIe VC \nA look at OSVVM co-simulation features and their use for constructing complex protocol verification component using PCIe as an example. It looks at the integration of the PCIe GEN1/GEN2 C model from the presenter’s pcieVHost project\, using OSVVM’s co-simulation capabilities\, to construct an OSVVM compatible Verification Component (VC)\, used like any other VHDL based VC\, but with additional features\, to drive 3rd party PCIe IP. An example of driving Altera’s Cyclone V Hard IP for PCI Express is discussed. \nBio: Engineer with 35+ years in R&D\, with experience in ASIC design\, FPGA\, and embedded software development. Currently working on developing open-source IP in areas such as co-simulation and system modelling. A collaborator on the OSVVM project\, adding and supporting its co-simulation capabilities and developing verification IP. \nAreas of experiences include logic IP for both ASIC and FPGA\, logic verification\, HPC\, processor systems\, networking (802.3 and proprietary)\, embedded software\, co-simulation technology\, software modelling of SoC systems\, data compression logic\, PCIe endpoint design\, cellular (3G and 4G)\, wireless (802.11 and 802.15.4). Joint or sole author on several logic IP related patents. \nDetailsYassine Eben Aimine\nSiemens \n×Yassine Eben Aimine\nYassine has more than 20 years’ experience in the EDA industry. Throughout his professional career\, Yassine has partnered with design and verification engineers to deploy the latest technologies in EDA tooling in the areas of design for test\, functional verification\, and functional safety. \nDetailsPhill J Payne\nPrincipal Digital Design Engineer\nNovomorphic \n×Phill J Payne\nPhill J Payne is Principal Digital Design Engineer at Novomorphic\, specialising in secure\, real-time FPGA and embedded architectures for edge AI. He is developing convolution acceleration and a modular hardware fabric that composes reconfigurable pipelines\, reduces memory pressure\, and delivers high-performance vision and inference at the edge. Across 26 years\, Phill has turned novel architectural ideas into deployable systems under tight power\, latency\, throughput\, and reliability constraints\, with deep experience in security-grade FPGA development and signal-processing workloads. Previously\, he delivered end-to-end FPGA firmware and software for advanced systems\, including a patented communications technique designed to operate in contested jamming environments\, later acquired by a major defence prime. He also built specialised training systems used in preparation for the London 2012 Olympic Games\, translating complex engineering into practical tools. \nDetailsGavin Lofts\nField Applications Engineer\nAltera \n×Gavin Lofts\nGavin Lofts is a Field Applications Engineer at Altera with 20+ years of experience in hardware\, embedded software\, and FPGA design. He has worked on systems ranging from biosensors to radio. \nPresentation: CI/CD and Git for Modern FPGA Development
URL:https://desn.org.uk/event/verification-semiconductors-futures-conference-uk-2026/
LOCATION:University of Reading\, Whiteknights PO Box 217\, Reading\, Berkshire\, RG6 6AH\, United Kingdom
CATEGORIES:DESN Event,DESN Promoted Event
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BEGIN:VEVENT
DTSTART;TZID=Europe/London:20260820T140000
DTEND;TZID=Europe/London:20260820T150000
DTSTAMP:20260511T121055Z
CREATED:20260511T121055Z
LAST-MODIFIED:20260511T121055Z
UID:23636-1787234400-1787238000@desn.org.uk
SUMMARY:Women in TechWorks: From Qubits to Confidence: Verifying Quantum Error Correction
DESCRIPTION:
URL:https://us06web.zoom.us/webinar/register/WN_jqtxyiffRPmeJwEHwqzaVA#new_tab
LOCATION:Webinar
CATEGORIES:TechWorks Event
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END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260826
DTEND;VALUE=DATE:20260827
DTSTAMP:20260422T090649Z
CREATED:20260422T090649Z
LAST-MODIFIED:20260422T090649Z
UID:23562-1787702400-1787788799@desn.org.uk
SUMMARY:TechWorks Semiconductors to Systems Summit 2026
DESCRIPTION:
URL:https://techworks.org.uk/techworks/tws2s26/#new_tab
CATEGORIES:DESN Event,TechWorks Event
ATTACH;FMTTYPE=image/jpeg:https://desn.org.uk/wp-content/uploads/2026/04/Featured-Image-1240-x-697-px-57.jpg
END:VEVENT
END:VCALENDAR