BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//DESN - ECPv6.17.1//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-WR-CALNAME:DESN
X-ORIGINAL-URL:https://desn.org.uk
X-WR-CALDESC:Events for DESN
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:Europe/London
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20220327T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20221030T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20230326T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20231029T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20240331T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20241027T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20250330T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20251026T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20260329T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20261025T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:UTC
BEGIN:STANDARD
TZOFFSETFROM:+0000
TZOFFSETTO:+0000
TZNAME:UTC
DTSTART:20210101T000000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;VALUE=DATE:20250521
DTEND;VALUE=DATE:20250522
DTSTAMP:20250723T082646Z
CREATED:20250314T140743Z
LAST-MODIFIED:20250723T082646Z
UID:22838-1747785600-1747871999@desn.org.uk
SUMMARY:FPGA Front Runners: Prototyping systems using FPGA
DESCRIPTION:Prototyping systems using FPGARegisterSponsored by Sundance\nWe’ve seen in today’s rapidly evolving industry\, FPGA prototyping plays a crucial role in ASIC design validation and early hardware/software integration. \nThe event will provide invaluable insights into how FPGA-based prototyping can de-risk development\, optimize performance\, and accelerate time-to-market. \nPotential Topics of Interest: \n\nEnsuring Confidence in ASIC Design Before Tapeout – Identifying and resolving potential design flaws before committing to silicon\nEarly Hardware/Software Integration – Bridging the gap between design and implementation to streamline development\nOvercoming Simulation Bottlenecks – Enabling longer\, more complex test scenarios that traditional simulations cannot handle\nAutomotive-Specific FPGA Applications – Exploring how FPGA prototyping is transforming the future of automotive electronics.\n\nWho Should Attend? \n\nASIC Designers – Validate and optimize your designs efficiently.\nAutomotive Engineers – See how FPGA enhances real-world automotive applications.\nEmbedded & System Architects – Leverage FPGA for early integration and debugging.\nTech Leaders & Decision-Makers – Stay ahead of industry trends and network with experts.\n\nAgenda \n\n\n\n\n\n09:00\nArrival and Registration\n\n\n09:30\nSundance – Multi FPGA solution for prototyping\n\n\n09:40\nChipflow -Fast FPGA prototyping with python for Automotive & Industrial\n\n\n10:00\nExostiv Labs- You can’t fix what you don’t see – A plea for visibility in FPGA\n\n\n10:30\nCadence- Use of Prototyping and Emulation in the semiconductor industry in 2025\n\n\n11:00\ndSpace- Enabling detailed HiL testing for electric drives with high speed FPGA\n\n\n11:30\nBreak\n\n\n12:00\nSiemens – How Veloce pro FPGA CS accelerates HW and SW verification closure ?\n\n\n12:30\nWeeteq-Utilising FGPAs to develop real time system response correction\n\n\n13:00\nEtas- The Importance of Deterministic Recompute when Developing ADAS Systems\n\n\n13:30\nSynopsys- EP-Ready Hardware-Assisted-Verification Platforms\n\n\n14:00\nLunch and Factory Tour\n\n\n\n\nSpeakers\nFrederic Leens\nCEO and founder\, Exostiv Labs \nFrederic is the CEO and founder of Exostiv Labs. Before establishing Exostiv Labs\, he worked as a designer and provider of design services for companies such as Barco\, NXP\, Philips\, Atos\, and ASML. This experience spanned various industries using semiconductors\, including finance\, medical imaging\, video and broadcast\, military\, and avionics. With over 20 years of expertise\, Frederic and his co-founders envisioned Exostiv Labs with the belief that properly instrumented FPGAs are crucial for enhancing product quality and streamlining design cycles. \nPresentation: You can’t fix what you don’t see – A plea for visibility in FPGAs \nAs FPGAs become more complex\, the design process has evolved in comprehensiveness. Interestingly\, tools—and sometimes engineers—have become highly specialised for specific tasks\, except for ‘debugging’\, which remains a somewhat vague concept that occurs throughout the entire design cycle. \nIn this brief talk\, we will examine the limitations of traditional methodologies and demonstrate that achieving orders of magnitude greater visibility is crucial for effective FPGA design and debugging. \nMichael O’Sullivan\nEngineering Group Director\, Cadence \nMichael O’Sullivan is an engineering director at Cadence with a focus on verification and is based in Edinburgh\, Scotland. . Michael has been with Cadence for over 27 years with various roles in sales\, marketing and design services. Prior to Cadence he was a design engineer at S3 Group in Dublin\, Ireland and at Philips in Eindhoven\, The Netherlands. Michael has an Masters of Engineering Science from the National University of Ireland. \nPresentation: Use of Prototyping and Emulation in the semiconductor industry in 2025 \nRob Taylor\nCEO\, Chipflow \nRob Taylor is driven by his passion for empowering individuals to unleash their creativity\, believing this will enable new products and business models that we can’t yet imagine. With over 20 years of commercialising open source software\, and two previous successful exits (Rev 10m)\, he combined startup leadership experience with deep technical knowledge to bring the vision\, strategy and delivery. \nPresentation: Fast FPGA prototyping with python for Automotive & Industrial  \nDr Philip Clarke\ndSPACE \nDr Clarke works for dSPACE\, a provider of solutions for the development and test of embedded control systems. He will talk about how FPGA technology supports high fidelity real time tests for complex controllers. \nPresentation: Enabling detailed HiL testing for electric drives with high speed FPGA models  \nFlemming Christensen\nSundance \nFlemming founded Sundance in 1989\, designing and building Multiprocessor solution based around INMOS’s Transputer. \n36 years later and not a lot has changed. \nSundance Multiprocessor Technology Ltd. was founded in 1989 and has thousands of man-years of experience operating as an Original Equipment Manufacturer (OEM). It offers a range of Commercial-of-the-shelf (COTS) boards for a broad range of customers. \nThey have in-house manufacturing equipment for electronics board and full test facilities. We run an ISO9001 Quality System to monitor all processes and have done since 1999. \nPresentation: Multi FPGA solution for prototyping  \nTaner Dosluoglu\nWeeteq \nDr Taner Dosluoglu\, Founder & CEO\nWeeteq \nSemiconductor Executive with decades of successful technology innovation and disruptive product introduction experience \nExperienced Semiconductor Executive with demonstrated history of successful technology innovation and disruptive product introduction in a Start-up environment as well as R&D teams within larger companies. Extensive experience in operations and product development as well as direct technical contributions in analog architecture\, circuits and system level design\, device and process innovations\, and publications in photonics\, semiconductor devices and circuits. \n• Previously: Sarnoff Corporation\, Tektronix\, SRI International\, Dialog Semiconductor\, Chaoyang Technologies\, Endura Technologies.\n• Ph.D. degree in Electrical Engineering in 1992 from Oregon Graduate Institute at Oregon Health Sciences University in Portland\, Oregon. \nJames Dickie\nEtas \nAn experienced product manager with detailed knowledge of emdedded software and development tools in the automotive and general embedded systems markets. \nGraham Harris & Amr EiDieb\nSiemens \nPresentation :How Veloce proFPGA CS accelerates HW and SW verification closure ? \nLearn how Veloce CS Systems are transforming the hardware assisted verification methodology to cope with the market transformation. Part of Veloce CS systems is the comprehensive prototype solution proFPGA CS aimed at maximizing the verification speed\, while offering a configurable capacity scalability from single FPGA to multi-blades/multi-FPGA’s configurations. \nXavier Mathes\nSynopsys \nXavier Mathes is a Principal Application Engineer at Synopsys. He is in charge of the Synopsys HAV products including HAPS\, EP and Synplify for Southern Europe and UK. Xavier previously worked at IBM\, Philips Semiconductor\, Synplicity\, and other semiconductor companies. His combined 28 years working in the industry has brought a wealth of knowledge and experience in the areas of semiconductor design and verification.\nXavier has a Master of Science in Electrical Engineer from CentraleSupelec. \nPresentation: EP-Ready Hardware-Assisted-Verification Platforms \n• Synopsys’ EP2 platforms for supporting emulation and prototyping are advanced solutions designed to accelerate the development and validation of complex semiconductor designs. These platforms provide a unified environment for hardware emulation and FPGA-based prototyping\, enabling engineers to efficiently verify functionality\, debug designs\, and validate system performance. EP2 platforms are highly scalable\, supporting designs ranging from small IP blocks to full-system SoCs. This scalability ensures flexibility for projects of varying complexity. The EP2 platforms utilize high-capacity FPGAs to create accurate prototypes of the design. \n• Prototyping allows enbles for real-world testing and validation\, including performance benchmarking\, power analysis\, and interoperability testing with external systems. \n• These platforms support high-speed interfaces and connectivity for seamless integration with external hardware and software environments. \n• The platforms support early software bring-up and validation\, allowing software teams to test drivers\, firmware\, and applications on the hardware prototype. \n• This reduces the risk of software-hardware integration issues and accelerates time-to-market.
URL:https://desn.org.uk/event/fpga-front-runners-prototyping-systems-using-fpga/
LOCATION:Rolls-Royce Control Systems\, 5000 Solihull Parkway\, Birmingham\, B37 7YH
CATEGORIES:DESN Event
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BEGIN:VEVENT
DTSTART;TZID=Europe/London:20250218T090000
DTEND;TZID=Europe/London:20250218T140000
DTSTAMP:20250124T191208Z
CREATED:20241220T183504Z
LAST-MODIFIED:20250124T191208Z
UID:19608-1739869200-1739887200@desn.org.uk
SUMMARY:FPGA FRONT RUNNER : Using AI in development and product for FPGA
DESCRIPTION:FPGA FRONT RUNNER : Using AI in development and product for FPGARegisterThe FPGA Front Runner event aims to bring together FPGA design and verification communities to discuss gate array-related topics. Participants can share knowledge\, learn about current developments\, and network with others. \nThe FPGA Front Runner event\, themed “Using AI in development and product for FPGA\,” is scheduled for Tuesday\, 18th February 2025\, from 9:00 AM to 2:00 PM at Renishaw\, UK. For more information and registration\, visit https://www.tickettailor.com/events/alpinumconsulting/1505991 \nA few speaker slots are still open for industry experts to share their insights. If you’re interested in presenting\, please contact Mike Bartley at mike.bartley@tessolve.com. \nAgenda (GMT) \n \n\n\n\n\nTime\nSpeaker\nDetails\n\n\n\n\n09.00\nArrival and registration\n\n\n\n09.30\nPete Leonard\, Renishaw\nIntroduction to Renishaw\n\n\n09.40\nGareth Richards\, AI Manager\, TechWorks\nTechWorks\n\n\n10.00\nAlexander Montgomerie Corcoran\, CEO\, Heronic\nHeronic\n\n\n10:30\nDavid Harold\, Chief Operating Officer\, RED Semiconductor\nRED Semiconductor\n\n\n11.00\nPedro Machado\, Senior Lecturer in Computer Science\, Nottingham Trent University\nNottingham Trent\n\n\n11:30\nRefreshment break\n\n\n\n12:00\nJeremy Bennett\, Embecosm\n\n\n\n12:30\nTBC\n\n\n\n13:00\nTBC\n\n\n\n13::30\nLunch\n\n\n\n14:00\nClose\n\n\n\n\n\n\nPrior to the main event\, we are pleased to offer a pre-event overview showcasing the key areas of discussion on Tuesday\, 21st Jan 2025. We kindly request your attendance for a 30-minute preview.
URL:https://desn.org.uk/event/fpga-front-runner-using-ai-in-development-and-product-for-fpga/
LOCATION:Renishaw\, Wotton-Under-Edge\, GL12 8JR\, United Kingdom
CATEGORIES:DESN Event
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BEGIN:VEVENT
DTSTART;TZID=Europe/London:20250206T083000
DTEND;TZID=Europe/London:20250206T170000
DTSTAMP:20250204T165348Z
CREATED:20241002T094032Z
LAST-MODIFIED:20250204T165348Z
UID:19565-1738830600-1738861200@desn.org.uk
SUMMARY:Trends in Semiconductor System Design
DESCRIPTION:Trends in Semiconductor System Design\nRegister for FREEThank you to our Sponsors\nThe Trends in System Design event\, hosted by DESN in Reading on February 6th\, will be open to both members and non-members. We will examine emerging trends in semiconductor system design\, with a particular focus on how AI/ML is being used in product design and the design flow. \nThe event will also address the challenges in designing IP to meet the compute intensive demands of AI\, including bandwidth and latency issues related to data access\, SoC design challenges\, and obstacles related to the latest technology nodes. \nAdditional topics will cover manufacturing\, testing\, yield challenges\, and the transition to chiplets. \nParticipants will also discuss the process of validating and signing off chips for production\, as well as cost and return-on-investment considerations.\nA second major focus will be on how to best leverage AI’s potential in design flows. Key discussions will explore where AI can be deployed for maximum benefit without introducing risks such as “hallucinations” or security vulnerabilities. \nPresentations will include insights from EDA companies on the features they are incorporating into their tools\, as well as contributions from users who are developing their own solutions. \n\n\n\n\n\nTime\nEvent\n\n\n\n\n09:00\nRegistration\, arrival and refreshments\n\n\n09:25\nIntroduction\n\n\n09:30\nKeynote: Chiplet Standards: A New Route to Arm-based Custom Silicon – Rob Dimond\, System Architect and Fellow\, Arm\n\n\n10:00\nThe Turkey Voting For Christmas – AI and the Verification Engineer – Andrew Bond\, Director – Silicon Verification\, Axelera AI\n\n\n10:30\nImec research: driving advancements in semiconductor technology – Bruno Jansen\, Regional Managing Director\, imec Cambridge UK\n\n\n11:00\nFrom Chips to Systems: Redefining Semiconductor Packaging and Integration – Dr. Jayakrishnan Chandrappan\, CSA Catapult\n\n\n11:30\nBreak\n\n\n12:00\nUsing Generative AI to Transform Chip to Data Center Design Flows – Rod Metcalfe\, Senior Product Management Group Director\, Cadence\n\n\n12:30\nAI-Enabling a Revolution in Chip Design Productivity – Loay Qteet\, Staff Application Engineer\, Synopsys\n\n\n13:00\nUnlocking the AI Advantage with Siemens EDA Products – Sathishkumar Balasubramanian\, Siemens\n\n\n13:30\nTechWorks AI Group  – Dr Mike Bartley\, Senior VP\, Tessolve\n\n\n13:45\nLunch followed by Close\n\n\n\n\nSpeakers\nSathishkumar Balasubramanian\, Senior Director of Product Management\, Marketing & Biz Dev\, Siemens \nUnlocking the AI Advantage with Siemens EDA Products \nWhat’s behind the excitement in the industry around AI? AI is impacting virtually every aspect of semiconductor design. Verifiably accurate AI solutions that “just work” deliver results that users can trust and accelerate schedules\, while reducing the overall resources needed for chip design and verification. At Siemens EDA\, we have successfully leveraged AI technologies to accelerate design and verification.  In this session\, we will provide an overview of state-of-the-art AI-powered solutions encompassing the entire Siemens EDA product portfolio. \nBiography \nSathish currently leads the product management and marketing organization for Solido Custom IC division and AI initiatives at Siemens. Sathish is an experienced product leader with over 20+ years of experience in EDA industry. Sathish’s focus is on bringing value to semiconductor ecosystem through innovative solutions. Sathish is proficient in scaling product portfolio growth and expansion of market share/revenue through relentless focus on data-based execution and thought leadership. \nPrior to Siemens\, Sathish held various product management\, strategic business development and corporate development roles for Cadence Design Systems and Synopsys. Sathish received his BS in Electronics & Communication from University of Madras\, MS in computer engineering from University of Alabama & MBA from UC Berkeley- Hass School of Business. \n\nAndrew Bond\, Director – Silicon Verification\, Axelera AI \nThe Turkey Voting For Christmas – AI and the Verification Engineer \nAs EDA embraces the new opportunities AI brings how will it change what we think of as verification.\nFrom tooling to coding\, from developing to debugging\, from team dynamics to hiring how might things be about to change\, and how can we be best prepared. \nBiography \nAndy has 25 years’ experience as a verification engineer and leader. After starting his career verifying processors for ST he was part of the foundation team for Icera before leading their verification team after the acquisition by NVIDIA.\nHaving since built and developed teams for Cirrus Logic and in fintech\, he is currently director of verification for Axelera AI\, helping solve the verification challenges of the next generation of AI chips. \n\nRob Dimond\, System Architect and Fellow\, Arm \nChiplet Standards: A New Route to Arm-based Custom Silicon \nA key challenge our partners are consistently looking to solve is: How can we continue to push performance boundaries\, with maximum efficiency\, while managing costs associated with manufacturing and yield? Today\, as the ever more complex AI-accelerated computing landscape evolves\, a key solution emerging is chiplets. \nChiplets are designed to be combined to create larger and more complex systems that can be packaged and sold as a single solution\, made of a number of smaller dice instead of one single larger monolithic die. This creates interesting new design possibilities\, with one of the most exciting being a potential route to custom silicon for manufacturers who historically chose off-the-shelf solutions. \nThis talk will describe the standards framework that Arm is building with our partners\, and the broader industry. Including our own specifications such as the Arm Chiplet System Architecture (Arm CSA)\, AMBA chip-to-chip and the role of industry standards such as UCIe. \nBiography \nRob Dimond is System Architect and Fellow at Arm. \nRob is a member of the leadership team for the Architecture and Technology group at Arm where his focus is future technology development for the infrastructure segment (servers & networking). \nPrior to Arm\, Rob was Chief Hardware Architect at FPGA computing start-up Maxeler. Rob holds degrees in Electronic Engineering and Computer Science from Imperial College\, London. \n\nRod Metcalfe\, Senior Product Management Group Director\, Cadence \nUsing Generative AI to Transform Chip to Data Center Design Flows \nDuring this session\, we will delve into advancements in Generative AI technology and its transformative impact on chip design technologies and methodologies. Hear how Generative AI is reshaping chip design\, optimizing chip performance\, and unlocking new possibilities for data center architecture. We will share current case studies\, and future trends that showcase the potential of Generative AI to drive innovation and efficiency in chip design workflows. \nBiography \nRod Metcalfe is a Senior Group Director in the Digital and Signoff product management team at Cadence\, responsible for digital implementation flows and artificial intelligence technology development. He has been involved with EDA for over 20 years\, gaining experience in all parts of the digital design flow from synthesis to sign-off. Before joining EDA\, Rod was a chip designer in the aerospace industry. \n\nDr. Jayakrishnan Chandrappan\, Head of Advanced Packaging\, CSA Catapult \nFrom Chips to Systems: Redefining Semiconductor Packaging and Integration \nThis talk explores the evolution of semiconductor packaging from traditional chip-level approaches to advanced system-level integration. It highlights cutting-edge trends such as 3D integration\, hybrid and heterogeneous integration\, and additive manufacturing\, which are transforming performance\, miniaturization\, and functionality. The session also addresses challenges like thermal management\, sustainability\, and supply chain resilience\, while emphasizing the role of co-design and digital twins in optimising system designs. Attendees will gain insights into how innovative packaging techniques are redefining the semiconductor industry’s capabilities and driving next-generation applications in AI\, IoT\, and beyond. \nBiography \nDr. Jayakrishnan Chandrappan\, Head of Advanced Packaging at CSA Catapult\, has over 25 years of global experience in the semiconductor industry. At CSA Catapult\, he spearheaded the establishment of a state-of-the-art compound semiconductor packaging facility and an expert team driving cutting-edge solutions in semiconductor integration for transformative applications\, including NetZero\, Future Telecoms\, and advanced sensing technologies. \nHe serves as an external advisory board member for the University of Bristol and the University of Leeds in the UK\, and as a Board of Studies member for Cochin University of Science & Technology (CUSAT) in India. His influence is further amplified through his active participation in industry bodies such as SEMI\, the Europe APC Committee\, and the International Microelectronics Assembly & Packaging Society (IMAPS) UK Chapter. \nPreviously\, Dr. Jay held technology leadership roles at Global Foundries Inc. (US)\, IME at A-STAR Singapore\, and as a Scientist for India’s Ministry of Electronics & Information Technology. A co-founder of two start-ups\, his accomplishments include Europe’s most prestigious Marie Skłodowska-Curie Fellowship and the Royal Society of Chemistry’s Emerging Technology Showcase Award.\nHe holds a PhD in materials engineering from University of LEEDS. \n\nBruno Jansen\, Regional Managing Director\, imec Cambridge UK \nImec research: driving advancements in semiconductor technology \nImec is the world’s leading non-profit semiconductor research centre\, dedicated to accelerating semiconductor innovation through collaboration. By pushing Moore’s Law to its limits\, imec continues to scale down the dimensions of logic devices while exploring new pathways at the system level. For decades\, imec has been at the forefront of innovation on the technology side of the ecosystem\, delivering differentiation that has benefited the entire semiconductor industry. To sustain its role in shaping the future of technology\, imec is broadening its focus to address system-scaling challenges in its roadmap. This presentation will provide insights into the research efforts imec is undertaking to further advance semiconductor technology. \nBiography \nBruno Jansen recently joined imec as Regional Managing Director of imec UK and Site Manager of imec Cambridge UK\, focusing on growing the imec Cambridge UK team and exploring collaboration opportunities across the UK. Bruno began his career at Motorola in Toulouse\, working on the design of 3G chipsets. In 2002\, he joined Arm in Cambridge\, initially as a CPU Design Verification Engineer\, and later managed the design verification activities for a CPU product line. He also oversaw operations for UK\, EU\, and US government-funded research programs at Arm Research before becoming Director of Operations for Enterprise Marketing at Arm in 2017. In 2022\, Bruno joined the startup Krai as Director of Operations\, where he was responsible for finance\, recruitment\, and legal compliance. \n\nLoay Qteet\, Staff Application Engineer\, Synopsys \nAI-Enabling a Revolution in Chip Design Productivity \nIn the rapidly evolving semiconductor industry\, an unprecedented productivity challenge is being confronted\, driven by a global talent shortage and increasing demands to accelerate chip design development while managing complexity and cost. This session will delve into the role of Artificial Intelligence as a transformative solution\, highlighting its potential to enable new levels of efficiency in the chip design process. \nBiography \nLoay Qteet\, Applications Engineering\, Staff Engineer at Synopsys\, with six years of experience in the Electronic Design Automation (EDA) field. He specializes in physical design\, RTLIIGDS flow development\, and EDA applications of Implementation and AI. Loay has played a key role in supporting various customer\, helping them to achieve their goals effectively and ensuring that Synopsys products meet their evolving requirements. \n\nDr Mike Bartley\, Senior VP\, Tessolve  \nTechWorks AI Group \nDr Mike Bartley has over 35 years of experience in software testing and hardware verification. He has built and managed state-of-the-art test and verification teams inside several companies (including STMicroelectronics\, Infineon\, Panasonic\, and the start-up ClearSpeed) and also advised several companies on organisational verification strategies (ARM\, NXP\, and multiple start-ups). He has been working on the application of artificial intelligence (AI) since using genetic algorithms in 1998 and now helps companies to adopt best practice AI in DV to improve the productivity and quality of their verification. \nMike successfully founded and grew a software test and hardware verification services company to 450+ engineers globally\, delivering services and solutions to over 50+ clients in various technologies and industries. The company was acquired by Tessolve Semiconductors where he is now Senior VP driving sales in Europe\, global DV strategies\, and R&D into adoption of AI and best practice. Tessolve is a a global company with 3000+ employees supporting clients in VLSI\, silicon test and qualification\, PCB\, and embedded product development in multiple vertical industries.
URL:https://desn.org.uk/event/trends-in-semiconductor-system-design/
LOCATION:Novotel Reading Centre\, 25b Friar Street\, Reading\, RG1 1DP
CATEGORIES:TechWorks Event
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BEGIN:VEVENT
DTSTART;TZID=Europe/London:20241121T093000
DTEND;TZID=Europe/London:20241121T140000
DTSTAMP:20241106T162946Z
CREATED:20241106T162854Z
LAST-MODIFIED:20241106T162946Z
UID:19581-1732181400-1732197600@desn.org.uk
SUMMARY:FPGA Frontrunner Event: FPGA Safety and Security
DESCRIPTION:FPGA Safety and Security\nAgenda (GMT) \n\n\n\nTime\nSpeaker\nDetails\n\n\n09.30\nArrival and registration\n\n\n10.00\nTobias Adryan\, Synopsys\nSecuring FPGAs Beyond the Bitstream\n\n\n10.30\nEspen Tallaksen\, EmLogic\nFPGA Requirements Tracking and the Requirements Traceability Matrix\n\n\n11.00\nAndrew Swirski\, Beetlebox\nSecuring FPGA Development Pipelines with DevSecOps\n\n\n11.30\nRefreshment break\n\n\n12.00\nIan Pearson\, Microchip Technology Inc.\nEU Cyber Resilience Act – Impacts on Business and Product Design\n\n\n12.30\nFlemming Christensen\, Sundance Multiprocessor Technology Ltd\nHow to secure supply of ‘COTS’ FPGA Modules\n\n\n13.00\nSpeaker TBD\n\n\n\n13.30\nLunch and networking\n\n\n14.00\nEnd\n\n\n\n\n\n\n\nNOTE \nPlease be aware that if you register for both the in-person and virtual events\, your physical ticket will be cancelled\, preventing access on the event day. \nWe also maintain a blacklist; individuals who register for the in-person event but fail to attend will be restricted from participating in future events. If you book a physical ticket but cannot attend then please cancel it in advance.\n \n\n\nLocation\nThe Cass Centre\, Shaftesbury Road\, Cambridge\, CB2 8BS \n \n\n\n\nSelect tickets\n\n\nNeed help?\nManage tickets
URL:https://desn.org.uk/event/fpga-frontrunner-event-fpga-safety-and-security/
LOCATION:The Cass Centre\, Cambridge\, CB2 8BS
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END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20240924T093000
DTEND;TZID=Europe/London:20240924T143000
DTSTAMP:20240904T135648Z
CREATED:20240904T114649Z
LAST-MODIFIED:20240904T135648Z
UID:19550-1727170200-1727188200@desn.org.uk
SUMMARY:FPGA Frontrunner: FPGA Verification Strategies
DESCRIPTION:FPGA Frontrunner: FPGA Verification Strategies\nThe FPGA Frontrunner event will be hosted by Rolls Royce at their venue in Solihull.\nThe event will focus on “FPGA Verification Strategies”. \nFor full details on this event and the agenda click the button below. \nFind out more
URL:https://desn.org.uk/event/fpga-frontrunner-fpga-verification-strategies/
LOCATION:Rolls Royce\, Solihull\, B37 7YP
CATEGORIES:FREE for All
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END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20240716T100000
DTEND;TZID=Europe/London:20240716T143000
DTSTAMP:20240715T091108Z
CREATED:20240618T133644Z
LAST-MODIFIED:20240715T091108Z
UID:19530-1721124000-1721140200@desn.org.uk
SUMMARY:FPGA Frontrunner: FPGA Technology and Methodology Roadmaps
DESCRIPTION:FPGA Frontrunner: FPGA Technology and Methodology Roadmaps\nThe FPGA Front runners is all about bringing together the FPGA & ASIC design communities to discuss all things FPGA\, to share knowledge\, find out what is going on and network with like minded people.\nThis event is hosted at a member site\, thus allowing us more space for networking. There will be a mini expo with members promoting their products and services to the group. A site tour will be arranged. \nWe are also inviting students from across the UK to the event\, to bring them closer to the community\, for them to understand about the world of FPGAs and meet our members who are actively seeking graduates. \nEveryone is welcome\, come along and get involved in what is becoming a vibrant community for FPGA & ASIC design engineers. \nRegisterSpeakers\nWe are happy to announce our speakers : \n\nFlemming Christensen\, Sundance\nHarald J Werner\, Efinix\nIan Pearson\, Microchip\nDirk Koch\, University of Manchester\nDavid Clift\, Aldec (FirstEDA)\n\nNote that when you sign up to this event you will be added to our TechWorks newsletter list. You can unsubscribe at any time. For more information please see the T&Cs below. \nHarald Werner\nEMEA Senior Sales Director and Managing Director\nEfinix Inc. \n28 years experience in the FPGA market in technical and Sales management position. 5 years at Actel as FAE\, 20 years in Technical and Sales management position at Lattice semiconductor\, 4 years in management position and managing director at Efinix GmbH \nIan Pearson\nPrinciple Embedded Solutions Engineer\nMicrochip Technology Inc. \nIan has held roles in MCU and MPU applications and also led the EU Wireless team for many years introducing Wi-Fi and Bluetooth into the embedded product lines. He has been involved with IoT since it’s inception and is an advocate of enhancing security in Connected Embedded Systems. To aid this he is active on several working groups in the IoT Security Foundation and has presented on security topics at several conferences. More recently he has returned to the FPGA space and supports Microchip clients on FPGA\, SoC and Security needs across multiple market segments.
URL:https://desn.org.uk/event/fpga-frontrunner-fpga-technology-and-methodology-roadmaps/
LOCATION:Microchip\, 720 Wharfedale Road\, Winnersh\, RG41 5TP
CATEGORIES:DESN Event
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BEGIN:VEVENT
DTSTART;TZID=Europe/London:20240429T100000
DTEND;TZID=Europe/London:20240429T163000
DTSTAMP:20240426T105915Z
CREATED:20240319T143205Z
LAST-MODIFIED:20240426T105915Z
UID:19409-1714384800-1714408200@desn.org.uk
SUMMARY:DESN FPGA Frontrunner AI/ML in FPGA
DESCRIPTION:FPGA Frontrunner AI/ML in FPGA\nThe FPGA Front Runners event will be hosted by Renishaw at their venue in Wotton-under-Edge.\nThe event will focus on “Using AI in development and product for FPGA”. \nIf you are interested in speaking at this event please email mike.bartley@techworks.org.uk \nTopics for talks: \n\nWhat AI support is being built into the FPGA fabrics?\nHow are they used?\nWhat input language is used and how does it find it’s way into the FPGA?\nHow is the AI trained?\n\nRegisterDirections\nWhen you arrive at Renishaw\, visitors should park in Car Park A (no charges) using Entrance A\, and register at the Innovation Centre.\nThe event will be hosted in Room Brunel 3\, but everything will be set in the Renishaw Innovation Centre. \nRenishaw MapSpeakers\nWe are happy to announce our speakers : \n\nAndrew Swirski\, Beetlebox Ltd\nJavier Carnero\, Samtec\nPete Leonard\, Renishaw\nChristos Bouganis\, Intelligent Digital Systems\nIan Pearson\, Microchip\nSuleyman Demirsoy\, Intel\n\nDetails will appear below as they become available. \nJavier Carnero\nField Applications Engineer\nSamtec \nJavier is a Field Applications Engineer for Samtec supporting customers across Europe on High Speed and RF product designs. Graduated on Electronics Product Development and having a good knowledge of physics he understands the signal channel from transceiver to receiver. \nPrior to Samtec he’s worked as FAE and Product Manager specialized on connectors with more than fifteen years of experience on the industry. \nAbstract \nFlyover technology\, low loss\, low latency interconnect solutions for AI/ML \nGrowing Artificial Intelligence and Machine Learning applications require faster FPGA SERDES for data processing which at the same time can benefit from new architecture topologies to support higher bandwidths to limit losses on the signal channel. \nCopper cable inside the server or edge computing can mitigate losses and latency at the same time they can reduce overall cost in the channel and design time carrying high speed signals from a chip adjacent or co-packaged connector to the front panel I/O and backplane. \n\nPete Leonard\nElectronics Design Manager – Group Engineering\nRenishaw PLC \nPete Leonard started his engineering career with EMI (later Thorn EMI) developing broad skills as an undergraduate within a number of defense projects\, specialising in Radar development including advanced airborne systems. Graduating in 1989 from UWE Bristol\, Pete went onto develop several high-speed data acquisition systems which included digital control\, incorporating FPGA devices. System validation was completed onsite at many MOD coastal locations in the UK. \nAbstract \nRenishaw is a FTSE 250 company with a broad range of metrology and manufacturing solutions and instrumentation\, including some healthcare products. The presentation will cover the sectors supported and an overview of some of the products and technology used. The use of AI is challenged including how products are designed\, and possible use of AI in products to improve performance – questioning how to control the environment in development and product performance. \n\nAndrew Swirski\nFounder and Managing Director\nBeetlebox Ltd \nAndrew Swirski is the founder and managing director of Beetlebox\, based in London. At Beetlebox\, he and his team created the first CI/CD platform focused on the embedded sector. Their platform has seen use within AI\,IoT\, 5G and the robotics sector. \nCaptivated by the potential of embedded systems to change the lives around us\, whilst as masters’ student at Imperial College London\, Andrew has been continually involved in the area\, whether as an engineer or as a business leader. He previously worked at Intel (Altera) on FPGAs for telecoms systems. \nAbstract \nWe are living in an unprecedented time for AI hardware. NVIDIA has promised the world’s most powerful chip with their new Blackwall-architecture GPUs. Hailo has debuted a new edge AI chip that is able to run generative AI with less than 5 Watts of power. Meanwhile FPGAs seem to constantly lag a model behind and require teams of experts to get results that compete with other chips. \nAt Beetlebox we are working with Imperial College London to solve the problem of constant obsolescence and the need for FPGA experts. By combining Imperial’s Automated Machine Learning tool\, MASE\, with our Development Operation (DevOps) platform\, BeetleboxCI\, our goal is to develop the first system capable of automatically building\, training\, deploying\, and operationalizing FPGA models that surpass GPUs in energy efficiency. We will explore why DevOps is an important factor and provide practical steps in building commercial systems. Join us as we discover how DevOps can unlock new possibilities in AI hardware innovation. \n\nIan Pearson\nPrinciple Embedded Solutions Engineer\nMicrochip Technology Inc. \nIan is a Principle Embedded Solutions Engineer at Microchip Technology Inc. He has held roles in MCU and MPU applications and also led the EU Wireless team for many years introducing Wi-Fi and Bluetooth into the embedded product lines. He has been involved with IoT since it’s inception and is an advocate of enhancing security in Connected Embedded Systems. To aid this he is active on several working groups in the IoT Security Foundation and has presented on security topics at several conferences. More recently he has returned to the FPGA space and supports Microchip clients on FPGA\, SoC and Security needs across multiple market segments. \nAbstract \nAI Solutions on Microchip FPGA and SoC \nAI/ML can be used in a wide variety of use cases. Some require specialist knowledge\, many can leverage available models to ease the development cycle. Microchip FPGA’s and SoC’s provide a platform for performant\, low power systems supported by AI/ML SDK’s and toolchains to create task optimised\, flexible\, scalable AI/ML solutions for Sensor and Edge devices. \n\nChristos-Savvas Bouganis\nProfessor of Intelligent Digital Systems\nImperial College London \nChristos-Savvas Bouganis is a Professor of Intelligent Digital Systems in the Department of Electrical and Electronic Engineering\, Imperial College London\, U.K. He is leading the iDSL group at Imperial College (https://www.imperial.ac.uk/idsl)\, with a focus on the theory and practice of reconfigurable computing and design automation\, mainly targeting the domains of Machine Learning\, Computer Vision\, and Robotics. \nAbstract \nDeep Neural Networks in the Embedded Space: Opportunities and Challenges \nThe talk will discuss the challenging problem of designing FPGA-based hardware accelerator for Convolutional Neural Networks targeting specifically the embedded space. The talk will focus on the opportunities that are provided when customisation of the design is possible through the use of reconfigurable computing\, and the challenges that a designer faces when maps large CNN models onto embedded FPGA devices. Furthermore\, details will be provided on our fpgaConvNet toolchain that addresses some of those challenges and enables the generation of high performance CNN accelerators achieving state of the art results. \n\nSuleyman Demirsoy\nSystem Architect\nAltera \nSuleyman Demirsoy is a System Architect in Altera / Intel Programmable Solutions Group. His interest and activity areas include AI\, DSP\, HPC and Cloud / DC workloads\, tools and platform optimization. He has been working with FPGAs for more than 20 years. \nAbstract \nAI on Altera FPGAs \nThe talk will provide a brief overview of Altera FPGAs’ AI capabilities and how our FPGA AI Suite helps embedded AI applications.
URL:https://desn.org.uk/event/technes-fpga-front-runner/
LOCATION:Renishaw\, Wotton-Under-Edge\, GL12 8JR\, United Kingdom
CATEGORIES:DESN Event
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BEGIN:VEVENT
DTSTART;TZID=Europe/London:20231207T183000
DTEND;TZID=Europe/London:20231208T010000
DTSTAMP:20230926T154249Z
CREATED:20230926T154249Z
LAST-MODIFIED:20230926T154249Z
UID:19272-1701973800-1701997200@desn.org.uk
SUMMARY:TechWorks Awards and Gala Dinner 2023
DESCRIPTION:TechWorks Awards and Gala Dinner 2023\nSecure your PlaceApply for an AwardWe are delighted to announce that our annual TechWorks Awards & Gala Dinner will be held on Thursday 7th December 2023\, at the Hilton Deansgate Hotel\, Manchester.\nThe event brings together hundreds of executives & professionals from across industry\, providing an excellent opportunity to network with industry leaders\, meet new clients or host existing ones whilst building brand awareness. At the dinner\, we announce the winners of the TechWorks Awards – celebrating achievements & behaviours conductive to a healthy & vibrant industry. \nThe TechWorks awards are open to all organisations active within the tech industry\, with award categories to fit a wide range of sectors. They are FREE to enter\, with a simple online process. \nWith a meal\, awards ceremony\, networking\, our guest speaker (comedian Alun Cochrane) and DJ\, dont miss out on the party of the year. \nVisit the TechWorks Awards and Gala Dinner website for full details.
URL:https://desn.org.uk/event/techworks-awards-and-gala-dinner-2023/
LOCATION:Hilton Deansgate Hotel\, 303 Deansgate\, Manchester\, Select a State or Province:\, M3 4LQ\, United Kingdom
CATEGORIES:TechWorks Event
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BEGIN:VEVENT
DTSTART;TZID=Europe/London:20231127T100000
DTEND;TZID=Europe/London:20231127T143000
DTSTAMP:20231116T131547Z
CREATED:20231106T171449Z
LAST-MODIFIED:20231116T131547Z
UID:19282-1701079200-1701095400@desn.org.uk
SUMMARY:FPGA Frontrunner Meet and Greet
DESCRIPTION:FPGA Frontrunner Meet & Greet\nSecurity at System Level\, and what security features we need in our FPGA to support this\nRegisterThe FPGA Front Runners event will be hosted by Thales at their venue in Reading.\nThe event will focus on “Security at System Level\, and what security features we need in our FPGA to support this”. \nIf you are interested in speaking at this event please email mike.bartley@techworks.org.uk \nTopics for talks: \n\nWhat is Security in FPGA-based Systems?\nWhat security features do we need our FPGAs to support this?\nExample applications and the implications for security\n(this is NOT supply-chain security)\n\nAgenda:  \n\n\n\n10:00\nRegistration\, arrival and refreshments\n\n\n10.30\nPeter Davies\, Thales – “Security in FPGA-based Systems”\n\n\n11:00\nMark Frost\, Intel – “Security in FPGA”\n\n\n11:20\nIan Pearson\, Microchip – “System and Device Level Security Considerations”\n\n\n11:40\nMaximilian Werner\, Efinix Inc – “Efinix FPGA Encryption solution”\n\n\n12:00\nFabio Caccamo & Chris Palmer from AMD\n\n\n12:30\nSimon Bowles\, Product Cyber Security Specialist\, Rolls Royce –  “RR’s product security goals and the context in which we use FPGAs”\n\n\n12:45\nAnkith Srinivasan\, Cirrus Rays Pvt Ltd  – “Physically Unclonable Functions (PUFs) in FPGA security”\n\n\n13:00\nWorking lunch in small groups – “FPGA use models and possible security concerns”\n\n\n14:00\nPresentations by each group\n\n\n14:30\nFinish refreshments/networking\n\n\n\n\nRegistration on the day via Thales’s front desk\nParking available – car registration needed
URL:https://desn.org.uk/event/fpga-frontrunner-meet-and-greet-3/
LOCATION:Thales\, 350 Longwater Ave\, Reading\, RG2 6GF\, United Kingdom
CATEGORIES:FREE for Members
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BEGIN:VEVENT
DTSTART;VALUE=DATE:20230914
DTEND;VALUE=DATE:20230915
DTSTAMP:20230728T084703Z
CREATED:20230714T094232Z
LAST-MODIFIED:20230728T084703Z
UID:19254-1694649600-1694735999@desn.org.uk
SUMMARY:Tessolve: Verification Futures
DESCRIPTION:Verification Futures\nRegisterThe conference is focused on hardware design verification.\nThe full conference program includes 17 talks covering verification challenges and solutions\, formal verification\, RISC-V\, System Verilog\, UVM for AMS Verification\, and VHDL Verification \nFull conference agenda below \n08:30 Arrival: Breakfast and Networking\n09:25 Welcome: Mike Bartley\, Tessolve Semiconductor Ltd\n09:30 Safety and Security challenges in hardware IP development\, Vivek Vedula\, ARM Ltd\n10:15 Ericsson’s Challenges of IP Development and Verification for Products with a Long Shelf Life\, Alex Duhovich\, Ericsson\n10:30 Cadence\n11:00 Refreshments and Networking\n11:30 Parallel tracks\n11:30 10 years of Verification Challenges Mike Bartley\, Tessolve\nRISCV CPU Verification – Opportunities and Challenges\, Divyang Agrawal\, Tenstorrent\, Inc\nValidation of Hybrid Architectures\, Suneil Mohan\, Intel Corporation\n11.30 What Can Formal Do For Me? Doug Smith\, Doulos\n11.30 Renesas’s Submission to the UVM-(A)MS working group\, Peter Grove & Steven Holloway\, Renesas\n12:30 Lunch and Networking\n13:30 A Modern Fable: The Lost Art of Processor Verification\, Larry Lapides (Imperas Software Ltd\n14:00 Advanced RISC-V Verification Technique Learnings for SoC Validation\, David Kelf\, Breker Verification System\n14:20 Improve the Quality of the Testbenches using specialized PySlint solutions\, Balram Naik Meghavath\, Broadcom ltd\n14:40 Hemendra Talesara\n15:00 Refreshments and Networking\n15:30 Parallel tracks\n15:30 Leveraging AMS verification and DMS verification for efficiency and quality in Mixed-signal designs\, Aditya Devarakonda\, NXP Semiconductor\nSigmasense\nMethodology focused testbench generation\, Benjamin Delsol – UVMGEN\n15:30 Using Non-Determinism with Formal? Doug Smith\, Doulos\n15:30 Faster than “Lite” Verification Component Development with OSVVM\, Jim Lewis\, SynthWorks Design Inc \nRegister now\nhttps://www.tessolve.com/verification-futures/vf2023-us/
URL:https://desn.org.uk/event/tessolve-verification-futures/
LOCATION:Austin\, Austin\, Texas
CATEGORIES:DESN Promoted Event
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BEGIN:VEVENT
DTSTART;VALUE=DATE:20230911
DTEND;VALUE=DATE:20230915
DTSTAMP:20230222T163325Z
CREATED:20230222T162920Z
LAST-MODIFIED:20230222T163325Z
UID:19124-1694390400-1694735999@desn.org.uk
SUMMARY:IMAPS-UK: EMPC23 - The 24th European Microelectronics & Packaging Conference
DESCRIPTION:IMAPS-UK: EMPC23 – The 24th European Microelectronics & Packaging Conference\nRegisterThe 24th European Microelectronics Packaging Conference (EMPC 2023) will return to the United Kingdom after 12 years and will be hosted at the Genome Centre in Hinxton\, near Cambridge from 11 – 14th September 2023. The website provides some initial information on the Conference\, including: \n\nProgramme Themes\nCall for Abstracts Timetable\nConference Schedule\nExhibition and Sponsorship\nThe Venue – Genome Centre\nTravel and Accommodation\n\nYou will attend presentations and posters from leading companies and academic institutions on emerging trends in electronics devices and associated technology. The event will introduce new materials and opportunities in the packaging of electronic devices and potential applications of systems. We are planning that EMPC 2023 will be run as a face to face event\, enabling attendees and exhibitors to network personally in the spacious surrounds of the Genome Centre. \nFind out more
URL:https://desn.org.uk/event/imaps-uk-empc23-the-24th-european-microelectronics-packaging-conference/
LOCATION:Genome Centre\, Hinxton\, Cambridgeshire
CATEGORIES:DESN Promoted Event
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BEGIN:VEVENT
DTSTART;TZID=Europe/London:20230718T120000
DTEND;TZID=Europe/London:20230718T163000
DTSTAMP:20230711T101522Z
CREATED:20230608T143327Z
LAST-MODIFIED:20230711T101522Z
UID:19192-1689681600-1689697800@desn.org.uk
SUMMARY:Engineering Trustworthy AI Workshop
DESCRIPTION:Engineering Trustworthy AI Workshop\nRegister TECHWORKS PARTNERED WORKSHOP: OPEN TO ALL\nAI innovation is accelerating and the legislative and governance responses are being rapidly assembled; but how should industry collectively respond to ensure a healthy balance between innovation and protection? \nTechWorks is keen to support the development of trustworthy AI systems. \nAt the workshop\, we will dive into what it takes to engineer trustworthy AI systems and how a collaborative effort can support that intent. We will be exploring the constituent parts such as design schemas\, methods\, approaches\, best practices\, frameworks\, and the potential for standards. Whilst the core theme will be “engineering AI systems”\, we cannot achieve our aim without understanding the wider contexts presented by the business\, policy\, legal and ethical themes as well. If your interest is in any of these areas – you should come along as we want to hear from you. \nThis is your opportunity to present your position and help forge the collective industry response. \nAs an outcome of the Trustworthy AI workshop\, we will:\n• Identify and prioritise areas for collective industry action.\n• Publish the results and start building appropriate industry-led groups.
URL:https://desn.org.uk/event/engineering-trustworthy-ai-workshop/
LOCATION:Caledonian Club\, 9 Halkin Street\, London\, SW1X 7DR
CATEGORIES:DESN Event
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BEGIN:VEVENT
DTSTART;VALUE=DATE:20230704
DTEND;VALUE=DATE:20230706
DTSTAMP:20230222T130018Z
CREATED:20230222T125913Z
LAST-MODIFIED:20230222T130018Z
UID:19120-1688428800-1688601599@desn.org.uk
SUMMARY:IMAPS-UK: CPE2023 – Centre for Power Electronics Annual Conference
DESCRIPTION:IMAPS-UK: CPE2023 – Centre for Power Electronics Annual Conference\nRegisterThe Centre for Power Electronics (CPE) Annual Conference will bring together the Power Electronics\, Machines and Drives Community to review the latest Research and Development that will impact the Electric Revolution.\nThis Conference will feature Invited Keynotes and Presentations from Leading Academics and Industrialists\, views of the Future Demands for Power Electronics and Drives and hearing about the latest research advances from the Centre for Doctoral Training in Sustainable Electric Propulsion and other Post Graduates and Post Doctoral Researchers. \nThe Conference will be run over 2 days to provide a comprehensive review of status of Power Electronics Research and Development\, including topics selected from: \n\nSemiconductor and Passive Devices\nPackaging and Interconnection\nConverters and Drives\nControl\, Test and Reliability\n\nPower Electronics and Drives Related Applications \nThe Conference will be preceded by a Workshop on Power Electronics Devices and Packaging – Training and Upskilling at the same venue on Monday 3 July 2023\, where attendees at the CPE 2023 Conference will receive a discounted rate. \nFind out more
URL:https://desn.org.uk/event/imaps-uk-cpe2023-centre-for-power-electronics-annual-conference/
LOCATION:University of Nottingham\, Jubilee Conference Centre\, Nottingham
CATEGORIES:DESN Promoted Event
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BEGIN:VEVENT
DTSTART;TZID=Europe/London:20230629T140000
DTEND;TZID=Europe/London:20230629T150000
DTSTAMP:20230607T082845Z
CREATED:20230606T160921Z
LAST-MODIFIED:20230607T082845Z
UID:19181-1688047200-1688050800@desn.org.uk
SUMMARY:Engineering Trustworthy AI
DESCRIPTION:Engineering Trustworthy AI\nRegister for FREE\nArtificial intelligence (AI) is one of the most transformative technologies of our time. It has the potential to solve some of the world’s most pressing problems\, however\, it also poses risks and in recent years as the field has exploded\, there have been growing concerns about those risks.\nElon Musk\, for example\, has warned that AI could be potentially more dangerous than nuclear weapons. With two prominent experts in the field\, Dr. Nick Allott and Professor Subramanian Ramamoorthy\, this Zoom webinar will explore how we can engineer AI systems so that they are trustworthy. \nJoin host Chris Bennison on Thursday 29th June.
URL:https://desn.org.uk/event/engineering-trustworthy-ai/
LOCATION:Webinar
CATEGORIES:DESN Event
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BEGIN:VEVENT
DTSTART;TZID=Europe/London:20230629T090000
DTEND;TZID=Europe/London:20230629T163000
DTSTAMP:20231106T171606Z
CREATED:20230512T162032Z
LAST-MODIFIED:20231106T171606Z
UID:19165-1688029200-1688056200@desn.org.uk
SUMMARY:FPGA Frontrunner Meet and Greet
DESCRIPTION:FPGA Frontrunner Meet & Greet\nRequirements Driven Development and Verification and the implications for Safety\nRegisterThe FPGA Front Runners event will be hosted by Renishaw at their venue in Wotton-under-Edge.\nThe event will focus on “Requirements Driven Development and Verification and the implications for Safety”. \nIf you are interested in speaking at this event please email mike.bartley@techworks.org.uk \nTopics for talks: \n\nHow to capture and verify requirements\nSpec creep and implementation changes\nHow to verify and ensure these are correctly addressed\nVerification as a review of the system\nImplications for safety\n\nAgenda:  \n\n\n\n08:45\nArrival and Registration\n\n\n09.30\nPete Leonard – Overview of Renishaw\n\n\n10:00\nRenishaw Engineering Talk\n\n\n10:30\nJon Wright\n\n\n11:00\nStewart Edmondson & Steve Drew\n\n\n11:15\nBreak\n\n\n11:45\nPuneet Goel\n\n\n12:15\nDiarmuid Maguire\n\n\n12:45\nJim Lewis\n\n\n13:15\nNick Tudor\n\n\n13:45\nClosing remarks\n\n\n13:50\nBuffet Lunch\n\n\n14:30\nAccess to demo area and Q&A\n\n\n\nExhibitors\nSundance Multiprocessor Technology Ltd\nSundance Multiprocessor Technology Ltd. was established in 1989. Our strategy is to produce a comprehensive range of well engineered products for the high-performance embedded processing market for Robotics\, Vision\, Motion and Sensor applications. \nTheir first products were designed for the parallel processing market. The product portfolio included PC add-in boards and modules. Sundance rapidly developed and built a wide range of processor modules and boards on industry standard form-factors\, like PC/104\, PXIe\, FMC and OpenVPX. The range included many special purpose modules and allowed Sundance to act as a ‘one-stop’ shop for system designers and manufacturers. \nToday\, the Sundance product range includes modular systems based on the Texas Instruments KeyStone range of multicore DSPs\, as well as the Xilinx Zynq multicore SoCs and Xilinx’s Series-7 FPGAs. \nhttps://www.sundance.com \n \nNanoES\nNanoES is unique in the industry in offering a range of solutions to customers looking for electronic manufacturing solutions\, electronic design capability or test solutions. By working with approved and vetted third party companies\, NanoES is able to identify the right partner for your products\, managing the whole process for you. \n​Having worked for a number of electronic manufacturing companies\, it’s clear that a large percentage of business is done with the customer never actually visiting the factory. Even with all transactions being done via email. But what happens if this process breaks down? \nNanoES bridges this gap\, by representing the suppliers directly\, we are able to link the customer to the supplier\, by finding the best solution and using trusted partners. NanoES manages the process for you\, leaving you the time to get on with more important business. \nhttps://www.nanoelectronicservices.com \nSpeakers\nNick Tudor\, CEO of D-RisQ Ltd.\nFollowing a full career as RAF Officer Engineer\, Nick has been working in software and high integrity systems for the past 2 decades. As co-Founder of D-RisQ\, he has worked in multiple sectors including aerospace\, defence\, automotive\, rail\, autonomous systems in air\, land\, sea\, nuclear decommissioning and cyber-security. He is one of only 3 UK nationals on the invite only panel for DO-178C advice and conducts audit and training in DO-178C and DO-254. D-RisQ is close to achieving the aim of being able to fully automatically formally verify from system requirements through to the binary using easily accessible tools and hence changing the way the world does software.. \nPresentation: In Silico AI \nWhen we undertake a task as humans\, we instinctively know how to undertake such a task (having had suitable experience and training). In order for a computer to do the same thing typically requires considerable computational power\, especially memory\, as well as time\, as the approach requires a sift through various combinations of actions to check whether a task is feasible and then to come up with a plan. Often the techniques try to optimise the plan requiring more time and resources. Having the ability to plan and to replan when something in the environment changes in real time without human intervention would be extremely useful. \nStewart Edmondson\, CEO of  UK Electronics Skills Foundation (UKESF)\nStewart Edmondson has been the CEO of the UK Electronics Skills Foundation (UKESF) since 2015.  The purpose of the UKESF is to tackle the Electronics’ sector skills shortage in a coherent way. Their aim is to: “encourage more young people to study Electronics and to pursue engineering careers in the technology sector”.  Stewart has a degree in Electronics and is a Chartered Engineer and Fellow of the Institution of Engineering & Technology.  He served for 24 years as an engineering officer in the Royal Air Force.  He is currently a Royal Academy of Engineering Visiting Professor at Aston University. \nPresentation: – UKESF’s current work and future initiatives \nThe recently published National Semiconductor Strategy stated that “skills are a fundamental building block underpinning the semiconductor sector at every stage. However\, from our engagement with industry it is clear that the UK needs to do more to sustain and grow the pipeline of talent available so that the sector has the people it needs to scale up” and that there was a need for “industry-led learning to ensure a robust pipeline of talent that meets their needs”. The presentation will update the audience on the UKESF’s current work and future initiatives\, in response. \nSteve Drew\, Owner of Nano Electronic Services Ltd.\nSteve has been working in the electronics industry for over 30 years\, promoting and selling semiconductors as well as design \, kitting and contract electronic manufacturing solutions. A knowledgeable and approachable industry veteran. Now running his own successful manufacturing agency\, helping customers with manufacturing challenges. Still keen to connect industry and academia and encourage the next generation through. \nPresentation: Promoting Soldering & Manual Skills to Students \nWorking alongside the IPC and Advanced Rework Technology\, Nano is involved in developing a series of roadshows to tour the UK to look to connect students and teenagers to the world of engineering. Focussing on soldering and electronics related manual skills to show youngsters there are alternative careers to be had in electronics \nDiarmuid Maguire\, Principal Engineer at Cambridge Consultants.\nDiarmuid Maguire is a Principal Engineer\, responsible for FPGA / ASIC development at Cambridge Consultants\, having joined in 2015. Diarmuid specialises in the implementation and verification of signal processing algorithms in RTL. During his time at Cambridge Consultants\, he has supported many international clients in their challenging FPGA & ASIC developments and has worked on verification and emulation of digital ASIC designs\, implementations of low power audio co-processors and beamforming and measurement systems for telecoms applications. \nPresentation: Developing ASIC quality and scale designs within FPGA timescales \nThe talk will focus on Cambridge Consultants’ experience producing ASIC quality and scale designs within FPGA timescales. It explores how different verification techniques allows for faster verification coverage of FPGA designs\, while still maintaining high confidence of meeting the requirements. \nJim Lewis\, Expert VHDL Trainer at SynthWorks Design Inc.\nJim Lewis is an innovator and leader in the VHDL community. He has 30 plus years of design and teaching experience. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice\, he has created designs for print servers\, IMA E1/T1 networking\, fighter jets\, video phones\, and space craft. Whether teaching\, developing OSVVM\, consulting on VHDL design and verification projects\, or working on the IEEE VHDL standard\, Mr Lewis brings a deep understanding of VHDL to architect solutions that solve difficult problems in simple ways. \nPresentation: OSVVM in a Nutshell \nOSVVM is an advanced verification methodology that defines a VHDL verification framework\, verification utility library\, verification component library\, scripting API\, and co-simulation capability that simplifies your FPGA or ASIC verification project from start to finish. Using these libraries you can create a readable\, powerful\, and concise testbench that will boost productivity for either low level block tests (unit tests) or complex FPGA and ASIC tests. \nPuneet Goel\, CTO at Coverify Systems Technology\nPuneet Goel is the co-founder and CTO at Coverify\, where he is crafting opensource tools\, libraries\, and VIPs for Hardware Verification. Currently\,Puneet is leading the hardware verification team at IncoreSemi to create verification solutions for Incore’s state-of-the-art RISC-V processors. Puneet has over twenty-seven years experience in the VLSI industry. He was an early adapter of SystemVerilog. He has also participated as a member of the IEEE technical committee for SystemC standard. He has multiple DVCon publications and a couple of patents to his credit. \nPresentation: Co-verification of SoCFPGA Designs \nVerification of hardware modules on an SoCFPGA based systems presents a unique chanllenge since the hardware modules mapped on the Progmmable Logic (FPGA Core) is tightly integrated with systems software that runs on the Hard Processor System (Embedded Processor). Embedded UVM (eUVM) is an opensource implementation of the IEEE 1800.2 Universal Verification Methodology standard that compiles natively to executable binaries that can be run on embedded processors enabling a novel hardware software cosimulation technique. During hardware design\, eUVM integrates seamlessly with Verilog\, VHDL\,SystemC as well as with Qemu based emulators. The same eUVM stimulus generators can later be seamlessly integrated on the SoCFPGA processor\, to facillitate validation of the hardware modules deployed on an SoCFPGA platform.
URL:https://desn.org.uk/event/fpga-frontrunner-meet-and-greet-renishaw/
LOCATION:Renishaw\, Wotton-Under-Edge\, GL12 8JR\, United Kingdom
CATEGORIES:DESN Event
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END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20230628T120000
DTEND;TZID=Europe/London:20230628T124500
DTSTAMP:20230414T104331Z
CREATED:20230414T091759Z
LAST-MODIFIED:20230414T104331Z
UID:19152-1687953600-1687956300@desn.org.uk
SUMMARY:Unwrapping the Patent Box for Automation & Technologies businesses
DESCRIPTION:Unwrapping the Patent Box for Automation & Technologies businesses\nRegisterTechWorks members new to Patent Box will benefit from a practical overview of how it works and the benefits it delivers\, while those already familiar with the regime can find out more about the synergies between Patent Box\, R&D tax relief and other innovation incentives.\nKey takeaways: \nLearn to identify untapped IP and R&D which may have been overlooked\nUnderstand what qualifies for relief\, including popular misconceptions\nQuantify what Patent Box could be worth to your business \nSpeakers: \nDavid Byrne\, Director\nAngela Banerjee\, Senior Tax Manager
URL:https://desn.org.uk/event/unwrapping-the-patent-box-for-automation-technologies-businesses/
LOCATION:Webinar
CATEGORIES:TechWorks Event
ATTACH;FMTTYPE=image/jpeg:https://desn.org.uk/wp-content/uploads/2023/04/fb-tw-webinar5.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20230504T110000
DTEND;TZID=Europe/London:20230504T114500
DTSTAMP:20230420T151115Z
CREATED:20230420T151042Z
LAST-MODIFIED:20230420T151115Z
UID:19161-1683198000-1683200700@desn.org.uk
SUMMARY:TechWorks & Envantage Partner Webinar – Power up your energy strategy\, market insights and cost reduction techniques
DESCRIPTION:TechWorks & Envantage Partner Webinar – Power up your energy strategy\, market insights and cost reduction techniques\nRegisterAre you are concerned that your business could be missing out on valuable energy discount schemes or want to know if you could pay less for your energy?\nJoin TechWorks and Envantage on Thursday 4th May for a focused webinar on how to find solutions for rising energy costs\, understand how the energy markets work and how Envantage can find the right strategy to help your business maximise potential savings\, hosted by industry experts Brian Gladwin and Meri Bortsvadze. \nTechWorks and Envantage have partnered together to provide members with exclusive access to sophisticated energy procurement solutions which are usually limited to very large energy users. Together we have created a bespoke TechWorks purchasing portfolio which offers flexible solutions and manages risks allowing members to future proof your businesses in volatile energy markets. \nWhy join this webinar? \n• Learn about a more strategic approach to procurement.• Understand which energy procurement options are available to you.• Learn about the new exclusive TechWorks purchasing portfolio and how it can benefit your business.• Understand the Energy Bills Discount Scheme and what extra support is available to the sector.• Gain an Insight to Energy Markets• Prepare for the next steps for your business.
URL:https://desn.org.uk/event/techworks-envantage-partner-webinar-power-up-your-energy-strategy-market-insights-and-cost-reduction-techniques/
LOCATION:Webinar
CATEGORIES:TechWorks Event
ATTACH;FMTTYPE=image/jpeg:https://desn.org.uk/wp-content/uploads/2023/04/Envantage-Webinar2.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20230330T083000
DTEND;TZID=Europe/London:20230330T160000
DTSTAMP:20230222T125205Z
CREATED:20230222T122428Z
LAST-MODIFIED:20230222T125205Z
UID:19110-1680165000-1680192000@desn.org.uk
SUMMARY:IMAPS-UK: Microtech 2023 – Advanced Packaging and Technology Trends
DESCRIPTION:IMAPS-UK: Microtech 2023 – Advanced Packaging and Technology Trends\nRegisterMicroTech 2023 will be an In Person Event on Thursday 30th March 2023 at University of Strathclyde Technology & Innovation Centre\, 99 George Street\, Glasgow\, G1 1RD\nMicroTech 2023 is the Annual IMAPS-UK Conference which will focus on Advanced Packaging and Technology Trends. This In Person Conference combines invited Keynotes and presentations from leading Industrial Companies and Research Institutions. The Conference will also include the IMAPS-UK Annual General Meeting (AGM). \nMicroTech 2023 will address the themes such as market analysis including current and future supply chain requirements\, providing examples of the implementation of advanced packaging technologies in challenging applications\, the development of sustainable materials and processes and latest advances in the assessment of quality and reliability. Advanced Packaging Technologies will not only be expected to demonstrate enhanced performance at the best possible cost\, but also improved efficiency\, reduced thermal impact and overall life cycle cost benefits. \nFind out more
URL:https://desn.org.uk/event/microtech-2023-advanced-packaging-and-technology-trends/
LOCATION:University of Strathclyde – Technology & Innovation Centre\, 99 George Street\, Glasgow\, G1 1RD
CATEGORIES:DESN Promoted Event
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END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20230329T090000
DTEND;TZID=Europe/London:20230329T163000
DTSTAMP:20230217T153812Z
CREATED:20230127T161331Z
LAST-MODIFIED:20230217T153812Z
UID:19081-1680080400-1680107400@desn.org.uk
SUMMARY:FPGA Frontrunner Meet and Greet
DESCRIPTION:FPGA Frontrunner Meet & Greet\nRegisterDESN is pleased to announce the next FPGA Front Runners event – to he hosted by Leonardo at their venue in Edinburgh on March 29th\, and will focus on FPGA Design using High Level Languages. \nThe FPGA Front runners is all about bringing together the UK FPGA & ASIC design communities to discuss all things gate array. Share knowledge\, find out what is going on and network with like-minded people. \nThis event continues the theme of hosting at a member site\, and allowing us more space for networking. There will be a mini expo with members promoting their products and services to the group. \nWe are also inviting students from across the UK to the event\, to bring them closer to the community\, for them to understand about the world of FPGAs and meet our members who are actively seeking graduates. \nLooking for Accommodation?\nThe Village Edinburgh Hotel is directly opposite Leonardo and boasts a Pub & Grill\, Starbucks\, Swimming pool and state-of-the-art gym.  To find out more and book\,  visit their website: \nhttps://www.village-hotels.co.uk/edinburgh \nSpeakers\nIain Pearson\, Pr. ESC\, Microchip Technology Inc.\nPrinciple Embedded Solutions Engineer at Microchip Ltd covering FPGA\, IoT\, Security and Cloud applications. Ian has been with Microchip for 23years covering everything from 8bit thro the introduction of the 16bit\, 32bit networking and wireless products. He managed the Wireless and Networking function team in Europe where he was an advocate of Secure by Design best practices. In the post covid era and the acquisition of Microsemi the opportunity to join the FPGA team arose allowing him to step back 25 years into his youth and re-discover FPGA all over again. \nPresentation: SmartHLS – C++ to Verilog Toolsuite \nHigh Level Synthesis tools can provide a significant improvement in productivity over RTL. This is especially the case in systems employing both a processor core and software in combination with FPGA logic. In this session we will look at where the Microchip SmartHLS toolsuite can be best a utilised to gain most benefit and where it is best to leave code running in software \nPadrig Guillard\, Sales Account Manager\, reflex ces\nWith nearly 15 years of experience in the FPGA market and a Hardware engineer background\, Padrig provides sales and technical to his customers in various high-end applications and markets. \nPresentation: Overview of JESD204B/C implementation in FPGA SoM \nKey Points:\n• Evolution of JESD204B/C support in reflex ces SoM products\n• How reflex ces allow JESD204B/C prototyping to reduce design risks and time to market \nDaniel Ogilvie\, Managing Director\, SingMai Electronics\nDaniel Ogilvie has over 40 years’ experience designing video products\, from no-compromise broadcast quality analogue video decoders and encoders\, to forensic image analysis products which can still be occasionally glimpsed on the CSI television programs. Daniel has worked for companies\, large and small\, in the UK\, Canada\, Thailand and Singapore. Daniel is a senior member of the IEEE. Outside of work\, Daniel Ogilvie is the author of three novels and has a Master’s degree in Art History. \nPresentation: Moving from Altera to Efinix FPGAs. \nKey Points: \n\nThe motivation for change – cannot buy Altera FPGAs – trying to buy dodgy parts from China.\nMoving our designs to Efinix – changes needing to be made.\nChanging the mindset – instantiating the PLLs and assigning pins.
URL:https://desn.org.uk/event/fpga-frontrunner-meet-and-greet-2/
LOCATION:Leonardo\, Edinburgh\, EH5 2XS\, United Kingdom
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END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20230321T130000
DTEND;TZID=Europe/London:20230321T140000
DTSTAMP:20230308T095153Z
CREATED:20230308T095123Z
LAST-MODIFIED:20230308T095153Z
UID:19136-1679403600-1679407200@desn.org.uk
SUMMARY:ZEISS: Quick methods for examination of p/n junctions in power devices webinar
DESCRIPTION:ZEISS: Quick methods for examination of p/n junctions in power devices webinar\nRegisterPower semiconductors are key components for transportation\, electrical grids\, and industrial drives. As the reliability of such devices can be affected by such phenomena as overcurrent\, desaturation\, and avalanche breakdown\, it is critical to be able to evaluate junction health and uniformity with simple methods. This webinar will demonstrate the value of analysing power semiconductors in FA with Passive Voltage Contrast (PVC) in the SEM as well as nanoprobing concepts such as Electron Beam Induced Current (EBIC). These techniques in combination examine not only the metallurgical p/n junction but also the corresponding depletion zones of the junction. An experimental method for examining the depletion zones in-situ as the gate bias will also be presented. \nFind out more
URL:https://desn.org.uk/event/zeiss-quick-methods-for-examination-of-p-n-junctions-in-power-devices-webinar/
LOCATION:Webinar
CATEGORIES:DESN Promoted Event
ATTACH;FMTTYPE=image/jpeg:https://desn.org.uk/wp-content/uploads/2023/03/zeiss-web2.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20221208
DTEND;VALUE=DATE:20221209
DTSTAMP:20220715T094939Z
CREATED:20220715T094939Z
LAST-MODIFIED:20220715T094939Z
UID:18886-1670457600-1670543999@desn.org.uk
SUMMARY:TechWorks Gala Dinner 2022
DESCRIPTION:WEBSITEBOOK NOWAWARDSWe are delighted to announce that our annual TechWorks Awards & Gala Dinner will be held on Thursday 8th December 2022\, at the Millennium Gloucester Hotel\, London.\nThe event brings together hundreds of executives & professionals from across industry\, providing an excellent opportunity to network with industry leaders\, meet new clients or host existing ones whilst building brand awareness. At the dinner\, we announce the winners of the TechWorks Awards – celebrating achievements & behaviours conducive to a healthy & vibrant industry. \nThis years Guest Speaker and Awards host is Paul Sinha who made his name on ITV’s hit quiz show\, The Chase\, where his quick wit and intelligence is highly popular with audiences. It is on the comedy circuit though that Paul comes into his own. \nApply for an award\nThe TechWorks Awards provide a fantastic showcase for excellence in the fast-paced tech industry – celebrating achievements & behaviours conducive to a healthy and vibrant industry. The 2022 awards are NOW open with award categories to fit all individuals and organisations active within the tech industry. All awards are completely FREE to enter\, with a quick and simple online process. \nThis year\, the awards are split into three main categories and are designed to suit individuals\, companies and organisation across the entire tech industry. They have historically attracted an impressive number of entries showcasing some amazing tech propositions. The 2022 Categories feature a strong range of awards from Automotive\, Manufacturing and IoT to Research Excellence. \nAlan Banks\, CEO\, TechWorks commented\, “Our Annual Awards are designed to be as inclusive as possible for both organisations and individuals across the tech industry. We are always delighted with not only the volume but the quality of entrants for the awards and we are looking forward to reviewing this year’s applications. \nThe awards have uncovered some truly ground-breaking businesses and inspirational individuals and we are looking forward to meeting many of the short-listed applicants and celebrating the Industry’s best at our gala dinner.”Applicants are invited to submit their FREE online entries from 12pm on Monday 4th July with the closing date for entries is Friday 30th September. To find out more and to apply for the awards – please visit the dedicated Awards website.
URL:https://desn.org.uk/event/techworks-gala-dinner-2022/
LOCATION:Millennium Gloucester Hotel\, 4-18 Harrington Garden\, London\, SW7 4LH
CATEGORIES:TechWorks Event
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END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20221115T093000
DTEND;TZID=UTC:20221115T160000
DTSTAMP:20221031T171013Z
CREATED:20221031T170628Z
LAST-MODIFIED:20221031T171013Z
UID:18976-1668504600-1668528000@desn.org.uk
SUMMARY:AI/ML and Students in Design Verification Day
DESCRIPTION:AI/ML and Students in Design Verification Day\nThe motivation for this event is to identify joint research projects between companies and universities with the objective of accelerating the application of AI (Artificial Intelligence) and ML (Machine Learning) in products and product development. We will also be trying to establish closer collaborations between companies and universities to promote our industry to student\,
URL:https://desn.org.uk/event/ai-ml-and-students-in-design-verification-day/
LOCATION:Thales\, 350 Longwater Ave\, Reading\, RG2 6GF\, United Kingdom
CATEGORIES:DESN Event
ATTACH;FMTTYPE=image/jpeg:https://desn.org.uk/wp-content/uploads/2022/10/technes-am.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20221109T120000
DTEND;TZID=UTC:20221109T160000
DTSTAMP:20220824T082438Z
CREATED:20220824T082255Z
LAST-MODIFIED:20220824T082438Z
UID:18951-1667995200-1668009600@desn.org.uk
SUMMARY:RF\, Micro & Milli Wave Network Event
DESCRIPTION:RF\, Micro & Milli Wave Network Event\nRegisterThis is the first RF Networking event for DESN.\nTo be held at the Huawei R&D Facility in Cambridge\, the aim of the group is to bring together design engineers from the RF\, Microwave and Milliwave communities together\, to collaborate and share knowledge as well as working to encourage the next generation of design engineers through. \nThis first meeting is to start to bring together companies to understand the needs and challenges for todays RF engineers. \nAll are welcome and we encourage the community to come together.
URL:https://desn.org.uk/event/rf-micro-milli-wave-network-event/
LOCATION:Huawei Technologies Research & Development (Uk) Limited\, Unit 101 Science Park\, Milton Road\, Cambridge\, CB4 0FY
CATEGORIES:DESN Event
ATTACH;FMTTYPE=image/jpeg:https://desn.org.uk/wp-content/uploads/2022/08/rf-event2-scaled.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20221025
DTEND;VALUE=DATE:20221026
DTSTAMP:20220511T141314Z
CREATED:20220511T141231Z
LAST-MODIFIED:20220511T141314Z
UID:18772-1666656000-1666742399@desn.org.uk
SUMMARY:Promoted Event: Hardware Pioneers Max 2022
DESCRIPTION:Hardware Pioneers Max 2022\nRegisterONE DAY WORTH ONE YEAR\nOur goal is to help you accelerate your success.\nAt Hardware Pioneers Max you have the unique opportunity to meet with a community of leading experts and suppliers that can help you to learn faster\, make better decisions and speed up your product development process. \nLearn\nGain actionable advice from the brightest minds in IoT on how to design\, build\, connect and manage your IoT product. Get up to date with the latest trends and advancements in the sector\, and learn how to avoid costly mistakes that can slow down your development process. \nConnect\nMeet other pioneering technical leaders\, product managers\, engineers and entrepreneurs who are building the next generation of IoT products. \nDo business\nDiscover the newest products and services to design\, build\, connect and manage your IoT devices. Find the latest and greatest hardware and software technologies to implement in your IoT device. Meet the partners that can help your \n\nFind out more at \nhttps://www.hardwarepioneers.com
URL:https://desn.org.uk/event/promoted-event-hardware-pioneers-max-2022/
LOCATION:London
ATTACH;FMTTYPE=image/jpeg:https://desn.org.uk/wp-content/uploads/2022/05/hardware-pioneers-event.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20221019T090000
DTEND;TZID=UTC:20221019T170000
DTSTAMP:20221004T103705Z
CREATED:20220715T150841Z
LAST-MODIFIED:20221004T103705Z
UID:18893-1666170000-1666198800@desn.org.uk
SUMMARY:FPGA Frontrunner Meet and Greet
DESCRIPTION:FPGA Frontrunner Meet & Greet\nRegisterDESN is pleased to announce the next FPGA Front Runners event – to he hosted by Rolls Royce at their Engine Controls facility in Solihull on October 19th . \nThe FPGA Front runners is all about bringing together the UK FPGA & ASIC design communities to discuss all things gate array. Share knowledge\, find out what is going on and network with like minded people. \nThis event brings something new to the group\, hosted at a member site\, and allowing us more space for networking. There will be a mini expo with members promoting their products and services to the group. \nWe are also inviting students from across the UK to the event\, to bring them closer to the community\, for them to understand about the world of FPGAs and meet our members who are actively seeking graduates. \nA factory tour will be arranged for the students\, there maybe some extra places available – so when registering\, please list your interest in a site tour. \nSpeakers will be announced nearer the time. \nEveryone is welcome\, come along and get involved in what is becoming a vibrant UK community for FPGA & ASIC design engineers. \nSpeakers\nDave Sanders\, Rolls-Royce\nDave Sanders is an Associate Fellow at Rolls-Royce specialising in the development of complex electronic hardware. He has 25 years’ experience working in the electronics industry\, with 22 of those developing the safety critical microprocessors that form the heart of the Rolls-Royce control systems for both aerospace and non-aerospace applications. \nRead More \nDave is a member of the European DO254 Users Group since 2012 and has contributed to various regulation working groups including co-authoring AMC 20-152A. He became a Fellow of the IET in 2018 and was awarded the Rolls-Royce Controls Gold Innovation Award in 2015 in recognition of the successful development of the sixth-generation safety critical microprocessor\, which has already accumulated over 20 million fault free flying hours. \nIn his spare time\, Dave is a keen runner and currently men’s captain for Lichfield running club. \n\nHarald Werner\, Efinix Inc.\nHarald Werner has over 30 years’ experience in the electronic industry. \nHe received an Dipl.- Ing (FH) at the FH Koblenz. \nHe started his career in 1987 at Siemens AG\, in 1992 he joined the EDA industry at Viewlogic Systems in 1995 he started the career in the semiconductor industry at Actel\, following in 2000 with Lattice Semiconductor and since 2020 he joined Efinix Inc. as European Sales Director. \nAdam Taylor\, Adiuvo Engineering & Training Ltd\nAdam Taylor is a world recognised expert in design and development of embedded systems and FPGA’s for several end applications. Throughout his career\, Adam has used FPGA’s to implement a wide variety of solutions from RADAR to safety critical control systems (SIL4) and satellite systems. He also had interesting stops in image processing and cryptography along the way. Adam has held executive positions\, leading large developments for several major multinational companies. \nRead More \nFor many years Adam held significant roles in the space industry he was a Design Authority at Astrium Satellites (Now Airbus Space) Payload processing group for six years and for three years he was the Chief Engineer of e2v Space Imaging\, being responsible for several game changing projects.\nAdam has held executive positions\, leading large developments for several major multinational companies. For many years Adam held significant roles in the space industry he was a Design Authority at Astrium Satellites (Now Airbus Space) Payload processing group for six years and for three years he was the Chief Engineer of e2v Space Imaging\, being responsible for several game changing projects. \nFPGAs are Adam ‘s first love\, he is the author of numerous articles and papers on electronic design and FPGA design including over 400 blogs and 25 million plus views on how to use the Zynq and Zynq MPSoC for Xilinx.\nAdam is Chartered Engineer\, Senior Member of the IEEE\, Fellow of the Institute of Engineering and Technology\, Visiting Professor of Embedded Systems at the University of Lincoln and Arm Innovator\, Edge Impulse Ambassador\, he is also the owner of the engineering and consultancy company Adiuvo Engineering and Training \n\nAmanda Brock\, OpenUK\nAmanda Brock is CEO of OpenUK\, the UK organisation for the business of Open Technology in the UK – open source software\, open hardware and open data – with a purpose of UK Leadership and International Collaboration in Open Technology. \nShe is a Board Member of the Open Source Initiative; appointed member of the Cabinet Office’s Open Standards Board; Member of the British Computer Society Inaugural Influence Board; Advisory Board Member\, KDE\, Planet Crust\, Sustainable Digital Infrastructure Alliance and Mimoto; Charity Trustee Creative Crieff and GeekZone; and European Representative of the Open Invention Network. \nRead More \nA lawyer of 25 years’ experience\, she previously chaired the Open Source and IP Advisory Group of the United Nations Technology Innovation Labs\, sat on the OASIS Open Projects and UK Government Energy Sector Digitalisation Task Force. Advisory Boards. She was General Counsel of Canonical for 5 years from 2008 and set up their legal function. \nAmanda was awarded the UK Lifetime Achievement Award in the Women\, Influence & Power in Law Awards 2022\, and included in Computer Weekly’s Most Influential Women in Tech Long list in 2021 and 2022 and in their UK Tech50 Influencers longlist for 2022. \nShe is the editor of Open Source\, Law\, Policy and Practice second edition being published by Oxford University Press in October 2022 and with open access thanks to the Vietsch Foundation. \nlinkedin.com/in/amandabrocktech/\n@openuk_uk @amandabrockUK \n\nAndy Darlington\, Renishaw\nAndy is a senior design engineer working within Renishaw’s encoder division on new product development. \nHe specialises in FPGA and VHDL with a particular interest in improving our team’s development processes. \nRead More \nPresentation Title:  Applying Continuous Integration to VHDL Development \nUsing VUnit and Azure DevOps to apply continuous integration and continuous delivery practices to VHDL development.
URL:https://desn.org.uk/event/fpga-frontrunner-meet-and-greet/
LOCATION:Rolls Royce\, Solihull\, B37 7YP
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END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20221013
DTEND;VALUE=DATE:20221015
DTSTAMP:20220511T141911Z
CREATED:20220511T141911Z
LAST-MODIFIED:20220511T141911Z
UID:18783-1665619200-1665791999@desn.org.uk
SUMMARY:Promoted Event: Frontier Deep Tech Conference
DESCRIPTION:Frontier Deep Tech Conference\nRegisterLEARN FROM THE BRIGHTEST MINDS IN THE WORLD\nGet a complete vision of DEEP TECH in all its diversity\, challenges and complexity through the most exciting TOPICS in today’s innovative technologies \nEurope’s leading deep tech event welcomes you to London\, 13-14th October 2022. \nQUANTUM COMPUTINGExplore the past\, present and future of quantum technologies and what they will bring to tomorrow’s society. \nAI & ROBOTICSUnderstand the implications of artificial intelligence and shape your innovation mindset with top level speakers. \nSEMICONDUCTORSDiscover the challenges of this sector to overcome and the benefits for society and our planet. \nCLIMATE & ENERGYSoftware alone can’t solve today’s energy and climate crisis: immerse yourself in new technologies that can. \nSPACE & TRANSPORTATIONLearn all form Smart Cities and IoT to logistics\, and from new propelling engines to satellites and eTVOL.! \nFind out more at \nhttps://frontierdeeptech.com/
URL:https://desn.org.uk/event/promoted-event-frontier-deep-tech-conference/
LOCATION:London
CATEGORIES:Promoted Event
ATTACH;FMTTYPE=image/jpeg:https://desn.org.uk/wp-content/uploads/2022/05/frontier-event.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20220713T093000
DTEND;TZID=UTC:20220713T170000
DTSTAMP:20220728T132609Z
CREATED:20220608T104348Z
LAST-MODIFIED:20220728T132609Z
UID:18794-1657704600-1657731600@desn.org.uk
SUMMARY:FPGA Frontrunner Meet & Greet
DESCRIPTION:FPGA Frontrunner Meet & Greet\nRegisterAgendaThe DESN FPGA Frontrunners event returns to The Moathouse – July 13th. Bringing together the UK FPGA & ASIC design communities to discuss all things gate array. Share knowledge\, find out what is going on and have a moan about the current state of affairs. All set within the beautiful Moathouse Inn. Lots of time to network\, have a coffee and at the end of the day a beer with colleagues and members with a shared common interest. \nThe event will be similar to that in March\, we will have a morning session of discussion around some key topics – followed by some interesting presentations from Gowin Semiconductor\, finding out a bit more about the products and roadmap\, represented by WPG – so will be interesting to hear how they plan to promote Gowin and their general plans for UK distribution. \nSomething close to everyone’s heart is staffing\, how to find new and existing design engineers and then when you have them\, how to keep them. We have IC resources along to share their thoughts and ideas on this. \nDirk Koch from Manchester University is going to explain all about their Open Source FPGA solution with their FABulous FPGA program. Then we have a talk from one of our sponsors – Synopsys. \nEveryone is welcome\, come along and get involved in what is becoming a vibrant UK community for FPGA & ASIC design engineers. \nImages from this event\nSpeakers\nNeil Dickins\, Co-Founder\, IC Resources\nIn 1999\, a weak link existed in the UK technology industry’s internal supply chain: there was no recruitment partner working in the best long term interests of the technology community. As a co-founder of IC Resources\, Neil started the business with the vision of helping individuals (our candidates) and companies (our clients) to achieve their long term ambitions within a prosperous and exciting sector… \nFIND OUT MORE×Neil Dickins\, IC Resources\nStaying true to our vision is the only real business decision he ever made or\, now\, makes. Candidates love to have someone acting as their personal ‘agent’ and customers always value expertise and insight-led services. Our hard work and industry commitment have enabled us to become the recognised recruitment partner to the global technology community. \nNeil now has the opportunity to focus on his professional passions\, including: 1) Ensuring that we maintain the highest level of quality and customer service while we grow the company. 2) Working with NMI as their link to government on visa and immigration issues. 3) Evangelising recruitment ‘best practice’ and how the right strategies can support business success and 4) Sponsoring and participating in high profile industry conferences and supporting UKESF\, the skills foundation. \nOn a personal level\, Neil still manages to get himself up and down the basketball court occasionally and has re-engaged with the Questors Theatre after 13 years away from ‘the boards’. He is also very intrigued by the intrinsic transformational potential of silly hats. \nPresentation: Find People? Great Problem! \nNeil will discuss the reasons for the industry-wide skills shortage\, followed by advice on strategies to maximise the probability of attracting and securing the best hires \nNigel Watts\, President EMEA\, WPG Holdings\nI Started my career in the Electronics industry as a trainee design engineer for GEC Semiconductors in 1978\, Joined Memec in 1983\, Sales\, Marketing and Management. Started Spectrum on December 1994 with Gamil Haddad\, a Rep company that we expanded to become the first pan European Representative business in 2003. Renamed Ismosys in 2008 went on to expand into India and USA. Sold to Astute Electronics in April 2021 to become President EMEA for WPG Holdings… \nFIND OUT MORE×Nigel Watts\, President\, EMEA\nI am passionate about demand creation and finding innovative and creative ways to solving customer issues and enhancing the experience for all parties concerned. \nPresentation: WPG – “Rising in the East\, Settling In The West” \nWhy have WPG decided to globalise and what advantages does it bring to European customers ? \n1. Access to emerging Asian / Chinese technologies – e.g Gowin ( and many others ). With control of the relationship both “locally” and internationally.\n2. Ability to track and also transport designs from Europe to Asian based CEM/EMS where we have long standing relationships.\n3. The financial backing of the world’s largest semiconductor distributor \, lines and inventory.\n4. A “wake up call” to others.\n5. Creative and innovative ways of delivering solutions and services to the design community. \nPiyush Sukhija\, Synopsys\nPiyush has been working for Synopsys for last 9 years and look after Verification SW activity in UK region. Working closely with sales to support customers\, collaborate with wider industry to understand complex verification challenges and work with Synopsys R&D to make improvement in Synopsys Verification offerings… \nFIND OUT MORE×Piyush Sukhija\, Synopsys\nPresentation: Accelerating FPGA verification \nDiscussion on Industry-leading design\, debug\, simulation and synthesis for accelerating verification closure
URL:https://desn.org.uk/event/fpga-frontrunner-meet-greet-2/
LOCATION:The Moat House\, Lichfield Street\, Tamworth\, B79 7QQ
CATEGORIES:Past Event Spotlight
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BEGIN:VEVENT
DTSTART;VALUE=DATE:20220705
DTEND;VALUE=DATE:20220707
DTSTAMP:20220408T141745Z
CREATED:20220408T114721Z
LAST-MODIFIED:20220408T141745Z
UID:18734-1656979200-1657151999@desn.org.uk
SUMMARY:IMAPS-UK Event: Centre for Power Electronics Annual Conference
DESCRIPTION:IMAPS-UK Event: Centre for Power Electronics Annual Conference\nRegisterThe Centre for Power Electronics (CPE) Annual Conference will bring together the Power Electronics\, Machines and Drives Community to review the latest Research and Development that will impact the Electric Revolution. \nThe attendees are offered exceptional value at attractive prices to participate in the Conference with support from the Centre for Power Electronics (www.powerelectronics.ac.uk)\, focusing on encouraging Students and Early Career Researchers to demonstrate their ideas and network with the PEMD community.
URL:https://desn.org.uk/event/imaps-uk-event-centre-for-power-electronics-annual-conference/
LOCATION:University of Warwick\, Gibbet Hill Road\, Coventry\, CV4 7AL\, United Kingdom
CATEGORIES:DESN Promoted Event
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BEGIN:VEVENT
DTSTART;VALUE=DATE:20220616
DTEND;VALUE=DATE:20220617
DTSTAMP:20220408T115507Z
CREATED:20220408T115157Z
LAST-MODIFIED:20220408T115507Z
UID:18744-1655337600-1655423999@desn.org.uk
SUMMARY:IMAPS-UK Event: PEPTUS Training Workshop
DESCRIPTION:IMAPS-UK Event: PEPTUS Training Workshop\nRegisterIMAPS-UK is organising a full-day Power Electronics Packaging Training Workshop to provide a basic understanding of the design\, testing and reliability issues involved in the assembly of power electronics components and modules that will form the basis of the Electric Revolution. \nThis workshop will focus on the fundamental aspects of power electronics packaging\, explaining the design considerations\, exploring the testing and reliability aspects and introducing the trends towards advanced packaging. This workshop will be complemented with a tour of the facilities at the CSA Catapult.
URL:https://desn.org.uk/event/imaps-uk-event-peptus-training-workshop/
LOCATION:CSA Catapult\, Innovation Centre\, Newport\, Duffryn\, NP10 8UL\, United Kingdom
CATEGORIES:DESN Promoted Event
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BEGIN:VEVENT
DTSTART;VALUE=DATE:20220519
DTEND;VALUE=DATE:20220520
DTSTAMP:20220419T095323Z
CREATED:20220419T094540Z
LAST-MODIFIED:20220419T095323Z
UID:18759-1652918400-1653004799@desn.org.uk
SUMMARY:ECS: The Electronic Component Show
DESCRIPTION:ECS: The Electronic Component Show\nRegisterThis new one-day event offers the opportunity for design engineers and purchasing professionals to network with electronic manufacturers\, distributors and service providers to source new products\, solutions and contacts. \nECS is a one day table top event that has been launched for those who design\, source and buy electronic components & associated services. \nOrganised by MMG Publishing\, publisher of Electronics Sourcing and eBOM. com\, the event aims to bring together the industry’s leading manufacturers and distributors with design engineers and purchasing professionals. \nOffering an informative dual seminar program\, this one day event is the place where ideas will be shared\, meaningful conversations will be had and business relationships can start or be strengthened. \nTo be held on Thursday 19th May 2022 at the Kassam Stadium (Oxford United FC) in Oxford; this central location is easily accessible with ample free car parking and local train stations.
URL:https://desn.org.uk/event/ecs-the-electronic-component-show/
LOCATION:Kassam Stadium\, Littlemore\, Oxford\, OX4 6DE
CATEGORIES:DESN Promoted Event
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