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SUMMARY:Promoted Event: Frontier Deep Tech Conference
DESCRIPTION:Frontier Deep Tech Conference\nRegisterLEARN FROM THE BRIGHTEST MINDS IN THE WORLD\nGet a complete vision of DEEP TECH in all its diversity\, challenges and complexity through the most exciting TOPICS in today’s innovative technologies \nEurope’s leading deep tech event welcomes you to London\, 13-14th October 2022. \nQUANTUM COMPUTINGExplore the past\, present and future of quantum technologies and what they will bring to tomorrow’s society. \nAI & ROBOTICSUnderstand the implications of artificial intelligence and shape your innovation mindset with top level speakers. \nSEMICONDUCTORSDiscover the challenges of this sector to overcome and the benefits for society and our planet. \nCLIMATE & ENERGYSoftware alone can’t solve today’s energy and climate crisis: immerse yourself in new technologies that can. \nSPACE & TRANSPORTATIONLearn all form Smart Cities and IoT to logistics\, and from new propelling engines to satellites and eTVOL.! \nFind out more at \nhttps://frontierdeeptech.com/
URL:https://desn.org.uk/event/promoted-event-frontier-deep-tech-conference/
LOCATION:London
CATEGORIES:Promoted Event
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DTSTART;VALUE=DATE:20220309
DTEND;VALUE=DATE:20220310
DTSTAMP:20220728T125841Z
CREATED:20220218T133517Z
LAST-MODIFIED:20220728T125841Z
UID:18335-1646784000-1646870399@desn.org.uk
SUMMARY:Synopsys: Early and Accelerated SoC Connectivity Verification using VC Formal Connectivity Checking App
DESCRIPTION:Synopsys: Early and Accelerated SoC Connectivity Verification using VC Formal Connectivity Checking App\nRegisterComplex bus protocols\, increased on-chip functionalities\, coupled with limited shared I/O resources\, result in complex wiring connections in SoCs with numerous muxing schemes.\nSimulation and structural analysis approaches require huge effort and may lead to bug escapes making them inefficient for SoC connectivity verification. Connectivity verification using formal techniques is exhaustive and helps making designs immune to connectivity bug escapes. \nFor over a decade\, VC Formal Connectivity Checking App has become an essential part of the verification toolkit used by leading edge technology companies. Its ability to scale with the ever increasing SoC design sizes\, its performance and ease of use\, and its optimized debugging capabilities\, make it a market leader in this space. \nJoin us to learn about SoC connectivity challenges and how Synopsys’ innovative technologies can help you catch and debug sneaky wiring mistakes early with 100% confidence and ease.
URL:https://desn.org.uk/event/synopsys-early-and-accelerated-soc-connectivity-verification-using-vc-formal-connectivity-checking-app/
CATEGORIES:Past Event,Promoted Event
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DTSTART;TZID=Europe/London:20220210T180000
DTEND;TZID=Europe/London:20220210T190000
DTSTAMP:20220408T091929Z
CREATED:20220121T134734Z
LAST-MODIFIED:20220408T091929Z
UID:18107-1644516000-1644519600@desn.org.uk
SUMMARY:Synopsys: 3DIC Design from Concept to Silicon
DESCRIPTION:Synopsys: 3DIC Design from Concept to Silicon\nREGISTERFor some high-performance computing (HPC) designs\, monolithic SoCs aren’t producing the scalability and yield that designers are looking for. New trends towards 3DIC design are emerging introducing new design challenges\, such as reliable die-to-die connectivity\, high bandwidth memory\, integration\, and 2.5D or 3D packaging options. This webinar will outline the different market trends for 3DIC designs and explain how designers can maintain such new trends to deliver their designs with optimized latency\, power\, performance\, and area. We will also demonstrate the construction of a 3DIC design and our 3rd generation HBM interposer auto-routing solution. \nAttendees will: \n\nLearn about considerations and trends for a more efficient 3DIC design integration\nFind out how protocols like HBM3 and Die-to-Die are influencing 3DIC designs\nSee a demo of a 3DIC design construction\n\nSPEAKERS\nKenneth Larsen is a product marketing director in the Silicon Realization Group at Synopsys. He is a versatile leader with a strong background in defining and executing product vision\, marketing strategy\, inspiring product development teams\, translating technology concepts into customer solutions\, developing high-performance global organizations\, conceiving and driving new and emerging products to scale from the ground up\, guiding marketing\, and enabling sales. Kenneth has a degree in electrical engineering and additional coursework in strategic growth at Columbia Business School\, and Artificial Intelligence at MIT Sloan School of Management. \nEric Means is an Applications Engineer in Hillsboro\, Oregon supporting Synopsys 3DIC Compiler users. He has worked with ASIC and EDA customers for 25 years at NEC\, Renesas\, & Synopsys. He has a BS in Electrical Engineering from Washington State University and an MS in Computer Engineering from the Oregon Graduate Institute. \n*This webinar is in partnership with SemiWiki and Synopsys*
URL:https://desn.org.uk/event/synopsys-3dic-design-from-concept-to-silicon/
CATEGORIES:Past Event,Promoted Event
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