BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//DESN - ECPv6.17.1//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-ORIGINAL-URL:https://desn.org.uk
X-WR-CALDESC:Events for DESN
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:Europe/London
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20210328T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20211031T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20220327T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20221030T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20230326T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20231029T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20240331T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20241027T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20250330T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20251026T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20260329T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20261025T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:UTC
BEGIN:STANDARD
TZOFFSETFROM:+0000
TZOFFSETTO:+0000
TZNAME:UTC
DTSTART:20210101T000000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20251106T090000
DTEND;TZID=Europe/London:20251106T173000
DTSTAMP:20260119T093201Z
CREATED:20250818T092753Z
LAST-MODIFIED:20260119T093201Z
UID:23065-1762419600-1762450200@desn.org.uk
SUMMARY:Designing the future: Tackling design challenges through collaboration
DESCRIPTION:REGISTERThank you to our Sponsors:  IC Resources   |    Synopsys   |   Cadence\nWomen in Techworks Sponsor: MicroTECH\nTechWorks DESN network aims to support the UK chip design industry by building communities of shared interest. This launch event will define new collaborative groups to address shared challenges and opportunities.\nAs chip complexity continues to accelerate\, designers face growing challenges in architecture design\, system scaling & integration and workflow. This hands-on event brings together chip architects\, designers and engineers to explore real-world pain points and application trends\, sharing lessons learned. The objective is to build ongoing collaboration supporting industry growth. \nWe will explore three contemporary themes during the event\, with a plenary discussion following each one to discuss the topics raised and identify relevant actions and initiatives for DESN to curate going forward. \nOUTLINE AGENDA \n\n\n\n\n\nTIME\nDETAILS\n\n\n\n\n09:00\nRegistration\n\n\n10:00\nTechWorks DESN Introduction – Scene setting and objectives\n\n\n10:10\nTHEME: The Future of Digital Design \nAs product roadmaps grow more demanding\, the design challenges are intensifying. How are chip designs evolving architecture\, workflow and methodology to stay ahead of the curve? \n\nNigel Toon\, Executive Chairman and co-founder\, Graphcore) \nMark Zwolinski\, Professor\, University of Southampton\n\n\n\n\n11:00\nDiscussion and CTA\n\n\n12:00\nNetworking Lunch\n\n\n13:00\nTHEME: Addressing the Chiplet Challenge \nTo achieve vendor and substrate-independent multi-die chiplet systems\, the industry must align on physical\, thermal\, and electrical compatibility\, adopt standard packaging techniques\, and develop sustainable business models. How can we make this a reality? \n\nYiru Zhong\, Market Development Specialist\, Arm\nPrashant Dubey\, Path Finding Researcher\, Imec Cambridge UK\nJohn Goodenough\, Professor of Microelectronic Systems\, University of Sheffield\n\n\n\n\n14:20\nDiscussion and CTA\n\n\n14:50\nBreak\n\n\n15:00\nTHEME: Applications of Digital Design \nMultiple breakthrough techniques are being driven by innovations in chip design. How can designers continue to deliver these market specific roadmaps at pace – from AI and intelligent mobility to high-performance\, energy-efficient computing. \n\nDorian Haci\, CEO and co-founder\, MintNeuro\nDr Jeremy Bennett\, Founder and Chief Executive\, Embecosm\n\n\n\n\n14:10\nDiscussion and CTA\n\n\n16:40\nRefreshments and Networking\n\n\n17:30\nClose\n\n\n\n\nNigel Toon\nExecutive Chairman and co-founder\, Graphcore \nNigel is a leading AI entrepreneur and is the founder and CEO of Graphcore.ai.  He sits as a Non-Executive Director on the board of UK Research and Innovation and sat on the UK Prime Minister’s Business Council. He has been recognized with numerous industry awards\, being ranked #1 on Business Insider’s UK Tech 100 and named as one of the ‘Top 100 entrepreneurs in the UK’ by the Financial Times. He was awarded a Doctor of Science degree from the University of Bristol and is the author of the best-selling book How AI Thinks. \nYiru Zhong\nMarket Development Specialist\, Arm \nWith more than twenty-five years in the technology sector\, Yiru Zhong has led market development for emerging technologies. Yiru’s work spans product strategy\, go-to-market design\, and partner development\, consistently aligning engineering roadmaps with market signals and operational execution. Having experienced through cycles of booms and busts in the last two decades\, Yiru brings disciplined judgment about what scales and what does not.\nYiru approaches innovation from the perspective of adoption: who will use it\, why it matters\, and how value is realised across ecosystems. This orientation enables clear separation of durable demand from transient hype. Drawing on professional and personal experience across Asia and Europe\, Yiru bridges diverse customer requirements\, regulatory contexts\, and supply chains to translate technical potential into commercial outcomes. \nDorian Haci\nCEO & Co-Founder\, MintNeuro \nDr Dorian Haci is an entrepreneur\, engineer and researcher with over a decade of experience in academia and industry. As CEO and Co-Founder of MintNeuro\, a spinout from Imperial College London\, he is pioneering the next generation of neural implants through innovative semiconductor technologies that enable safer\, smarter and more scalable brain interfaces. He also serves as an Enterprise Fellow at the Royal Academy of Engineering and a Visiting Researcher at Imperial\, where he earned his PhD in microelectronics for implantable medical devices. Under his leadership\, MintNeuro has secured multi-million-pound funding from the UK’s NIHR\, ARIA and Innovate UK to support R&D collaborations with world-leading research institutes and medical device companies. His work focuses on advancing chip-based solutions for neurological conditions such as epilepsy\, Parkinson’s and dementia. \nABSTRACT×When Chips meet the Brain: designing the next generation of neural interfaces\nDigital technology has evolved through successive generations of interfaces. Mainframes brought computing into institutions\, personal computers to the desk\, smartphones to the hand\, and wearables to the body – each step enabled by advances in semiconductor design. A similar path has shaped implantable medical technology. Early pacemakers and open-loop stimulators evolved into sensory prostheses and adaptive neuromodulators\, reflecting the same semiconductor progress from transistors to integrated circuits\, ASICs\, and systems-on-chip. \nWe are now entering a 5th generation where these trajectories converge. Neural interfaces are beginning to restore communication\, independence\, and quality of life for people with neurological conditions\, while opening new possibilities for interaction between humans and technology. Implantable systems face demanding requirements: they must be miniaturised\, ultra-low-power\, biocompatible\, hermetically sealed\, and reliable for years within a biological environment. Meeting these challenges depends on semiconductors that integrate multiple functions within millimetre-scale platforms. This requires new materials\, heterogeneous integration\, new architectures and computing paradigms for adaptive\, closed-loop operation. \nAt MintNeuro\, we develop semiconductor technology specifically for neural implants. Our purpose-build chip platform provides modular building blocks for functions like sensing\, stimulation\, and processing\, enabling medical device companies and researcher to design smaller\, safer\, and scalable systems. By co-designing chips and devices with academic and industrial collaborators\, we aim to bridge electronics and biology through shared design and engineering. This convergence defines a new frontier for semiconductor design – one where performance\, safety\, and collaboration meet. \nJohn Goodenough\nProfessor of Microelectronic Systems\, University of Sheffield \nInspiring the next generation of talented microelectronic system design engineers\, researchers and educators. Driving new programs in research and curriculum that address technology and skills gaps in the Semiconductor Industry. Focus areas on the architecture\, integration automation and assurance of secure\, power-efficient integrated semiconductor systems. \nPreviously\, experienced Global Technology Executive\, Systems and SoC Solutions architect. With broad view across multiple Information Technology\, Secure Distributed Embedded Systems\, System on Chip (SoC) and Electronic Design Automation. \nDr Jeremy Bennett\nFounder and Chief Executive\, Embecosm \nEmbecosm was founded in 2008 by Dr Jeremy Bennett\, an expert on hardware modeling and embedded software development. Previously Dr Bennett was Vice President of ARC International plc\, following their acquisition of Tenison Design where he had been CEO and CTO. \nDr Bennett is author of the popular textbook\, “Introduction to Compiling Techniques” (McGraw-Hill 1990\, 1995\, 2003) and holds an MA and PhD in Computer Science from Cambridge University. \nMark Zwolinski\nProfessor\, University of Southampton \nMark Zwolinski is a Professor in the School of Electronics and Computer Science\, University of Southampton. He has published over 220 journal and conference papers and 3 books. He has supervised 39 PhD students to completion. \nHis research interests include systems modelling\, design for reliability\, and heterogeneous computing. He is an Associate Editor of IEEE Transactions on VLSI. He has served on the programme committees of DATE\, DAC\, CODES+ISSS and ETS. He has also contributed to IEEE standards in test\, VHDL and Verilog. \nMark Zwolinski is a Fellow of the IET and BCS\, and a senior member of IEEE and ACM. He is a member of the Academic Accreditation Committee of the IET. \nABSTRACT×Adiabatic Logic Design for Low-Cost\, Low-Energy Processing\nFlexible electronics\, fabricated using\, for example\, Thin-Film Transistors (TFTs) are a promising technology for applications such as AI/ML at the edge. Such technologies often only implement N-type transistors and thus require pull-up logic\, which is very inefficient in terms of energy. \nAdiabatic logic was proposed as a low power technology several decades ago. The underlying principle is that logic gates should only be turned on as they are needed and not turned off when they are active. This is achieved by using the clock\, or multiple clock phases\, as the power supply for logic gates. Adiabatic logic designs have been proposed that use both NMOS and PMOS transistors\, but designs that use only NMOS transistors are possible. In order to achieve the promised energy efficiency\, however\, such circuits are very slow compared with modern CMOS technologies\, which means that adiabatic logic has never achieved widespread acceptance. On the other hand\, modern flexible electronics operate at relatively low frequencies. Thus\, adiabatic logic may prove to be an appropriate technique for low power design in these technologies. \nIn this talk we will look at how adiabatic logic can be implemented in an N-type technology. We will look at some circuit designs and show that the energy-efficient clock speeds of adiabatic logic are compatible with the clock speeds achievable in flexible electronics. Nevertheless\, formidable design challenges exist. Existing design tools are not compatible with adiabatic design styles. Signal paths need to be carefully balanced in order that the correct clock phases activate logic in sequence. In principle\, some energy recovery is possible in adiabatic circuits\, but we need to consider on-chip energy storage. \nPeter Birch\nHardware Lead Engineer\, Fractile \nPeter Birch is a Hardware Lead Engineer at Fractile\, working in the silicon team to deliver industry leading throughput and efficiency for AI inference workloads. Through past experience at VyperCore and Graphcore\, he has worked with cutting-edge approaches to design\, verification\, and infrastructure and advocates for the use of open source tooling and methodologies in commercial ASIC development. \nPrashant Dubey\nPath Finding Researcher\, Imec Cambridge UK \nPrashant Dubey is a pathfinding researcher at Imec Cambridge UK\, where he is engaged in STCO on 2nm nanosheets/forksheets and CFETS. This involves 3D and wafer level integration of TByte scale SRAMs\, integrated buck converters for high voltage to low voltage vertical power delivery\, back-side clock generation and routing and high-speed interconnects (petabytes/sec)\, for AI driven HP Compute in Data-Center applications. Prashant received his BE degree from Gorakhpur University\, India in 1998 and MS research degree from IIT Delhi\, on hyper-coupled ring oscillators. From 1998 to 2012 he worked for STMicroelectronics India as a Senior Design Expert\, Analog & RF\, where he designed embedded SRAMs and ROMs\, memory and SoC DFT\, analog and digital integer-N and fractional PLLs and oscillators. From 2012 to 2017 he worked for Synopsys India and led the research on low voltage SRAM architectures in 16-7nm FinFETs on write/read assist. From 2017 to 2018 he worked with Xilinx India on 3D FPGA architectures and in 2018\, joined ARM Cambridge UK and then MediaTek UK where he worked on voltage droop mitigation sensors and 5G mmW\, sub-100fs integrated jitter PLLs with dead-zone less 1st-order noise-shaped TDC architecture. He has produced\, 25 US Patents and 14 IEEE publications. \nABSTRACT×Collaborative Ecosystem as a key enabler of AI Driven Wafer Scale Data-Centres Research\nAt IMEC Cambridge UK\, we are currently involved in the pathfinding research of the xTCO in the domain of AI workload driven compute systems. Next-generation systems will need to handle AI models with over 100 trillion parameters or more\, driving an exponential increase in compute capacity demand. The power requirements of these systems are skyrocketing. Data centres consume between 2% and 3% of the world’s electricity (approx. 400 Terawatts)\, according to the International Energy Agency. AI enabling data-centres can consume a massive power of at least 500MW which is enough electricity to supply two million homes. As put forth by Feryal Clark\, Minister for AI\, “Just like coal and steam powered our past\, AI is powering the future. A significant portion of this energy is consumed by the data movement between isolated racks within data centres. Wafer-scale compute (WFC) aims to reduce this power consumption by integrating and packing compute and memory elements as close as possible. The key integration challenges in a WFC are driven by embedded memories which can be an SRAM\, DRAM or any other form of emerging memories\, in the orders of Terabytes\, achieving latencies in the order of Petabytes/second\, power delivery through vertical power delivery systems at high voltages with 500V to 1V integrated voltage converters in the order of 5 to 10Watts/mm2 and thermal extraction of a similar order. Advanced packaging is therefore another challenge due to heterogeneous integration of chiplets\, which involves advanced materials and their fusion with silicon e.g. Glass\, GaN etc. and is now playing a critical role in system design. Apart from advanced materials\, advanced packaging also involves new technologies like TSVs and hybrid bonding and their associated modelling for design co-optimization. IMEC pathfinding research has played a vital role in advancing the industry leading technology roadmap e.g. Gate-All-Around transistors\, Back-Side power delivery and continues to do so atleast with a decade margin between the conception and the productization. To convert brilliant but challenging ideas into successful products\, collaborative framework is pivotal at Imec. Imec Cambridge UK has been established to enable such a collaborative framework with UK Academia\, Start-ups and Industries to enable AI workload driven compute system. Our talk is aimed at the audience who are facing similar challenges in the field of wafer scale compute and see a value addition in such a collaborative framework with Imec.
URL:https://desn.org.uk/event/designing-the-future-tackling-design-challenges-through-collaboration/
LOCATION:Hilton London Olympia\, 380 Kensington High St\, London\, W14 8NL
CATEGORIES:Past Event
ATTACH;FMTTYPE=image/jpeg:https://desn.org.uk/wp-content/uploads/2025/08/Featured-Image-2025-10-10T152433.080.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20220323T093000
DTEND;TZID=Europe/London:20220323T183000
DTSTAMP:20220408T090730Z
CREATED:20220125T175606Z
LAST-MODIFIED:20220408T090730Z
UID:18119-1648027800-1648060200@desn.org.uk
SUMMARY:FPGA Frontrunner Meet & Greet
DESCRIPTION:FPGA Frontrunner Meet & Greet\nAgendaNMI is all about sharing knowledge and creating communities. The FPGA Front Runners exists to share knowledge\, best practice and to create a community around FPGAs and ASIC development.\nEach event is about networking\, meeting colleagues\, grabbing a coffee and some cake and listening to presentations from suppliers and your peers. \nThe event is designed to create a community of likeminded engineers\, and is run by members for members and the subjects and presentations are chosen by the members\, so remain valid. \nThe ultimate aim is to create a better awareness of FPGAs & ASICs in the UK\, drive best practice\, identify common issues and challenges and work together to resolve them. This first event is designed to bring together the community\, discuss the current market conditions around FPGAs\, the issues and technical challenges each member needs to overcome. Look at the skills shortages and what is needed to improve the engineers use of FPGAs. Everyone is welcome and we encourage you to attend and get involved. \nEvents are planned to run quarterly\, with other events or webinars in between as suggested by the community. \nAdam Taylor\nAdiuvo Engineering & Training Ltd \nAdam Taylor is a world recognised expert in design and development of embedded systems and FPGA’s for several end applications. \n×Adam Taylor\, Adiuvo Engineering & Training Ltd\nAdam Taylor is a world recognised expert in design and development of embedded systems and FPGA’s for several end applications. Throughout his career\, Adam has used FPGA’s to implement a wide variety of solutions from RADAR to safety critical control systems (SIL4) and satellite systems. He also had interesting stops in image processing and cryptography along the way. Adam has held executive positions\, leading large developments for several major multinational companies. For many years Adam held significant roles in the space industry he was a Design Authority at Astrium Satellites (Now Airbus Space) Payload processing group for six years and for three years he was the Chief Engineer of e2v Space Imaging\, being responsible for several game changing projects.\nFPGAs are Adam ‘s first love\, he is the author of numerous articles and papers on electronic design and FPGA design including over 400 blogs and 25 million plus views on how to use the Zynq and Zynq MPSoC for Xilinx. \nAdam is Chartered Engineer\, Senior Member of the IEEE\, Fellow of the Institute of Engineering and Technology\, Visiting Professor of Embedded Systems at the University of Lincoln and Arm Innovator\, Edge Impulse Ambassador\, he is also the owner of the engineering and consultancy company Adiuvo Engineering and Training. \nPresentation: PYNQ – FPGA with Python \nRead MoreSteve Drew\nNMI Electronic Systems \nSteve has over 30 years of semiconductor\, electronics and design industry experience. \n×Steve Drew\, NMI Electronic Systems\nSteve has over 30 years of semiconductor\, electronics and design industry experience. Starting his career at Avnet\, he became one of their youngest product managers – looking after Xilinx for the UK. Steve subsequently worked at a number of niche component distributors\, promoting and selling \, technical component solutions\, ranging from video codecs\, power products and FPGAs\, through to connectivity and display solutions. FPGA’s became his thing in the 1990’s and Steve worked with all the FPGA manufacturers except Altera. Moving on from component distribution Steve has worked at component kitting and PCB assembly companies\, and having worked for large multinational companies and smaller privately owned businesses\, has given Steve a wide view of the component market place and the challenges faced by companies\, and having run his own manufacturing consultancy since 2020 has given him an understanding of the small business sector. \nSteve loves the electronics industry and technology in general\, is passionate about UK manufacturing and how we can build more here instead of losing it to offshore competition\, is a champion of startup’s and innovation. And if you want an opinion on something\, just ask him \nRead MoreTony Holmes\nCadence \nTony started his career at Digital Equipment in the design & development of Computer Special Systems then moved into the Design and Development of High Performance Bridge Routers. \n×Tony Holmes\, Cadence\nTony started his career at Digital Equipment in the design & development of Computer Special Systems then moved into the Design and Development of High Performance Bridge Routers\, followed by creating a System Level Testing group to test these Bridge/Routers in complex networking scenarios. \nTony moved to Quickturn Design Systems before Quickturn merged with Cadence Design Systems. Tony is a Technical Director at Cadence Design Systems with a long history of focussing primarily on HW based verification using Emulation and FPGA Prototyping. \nTony has responsibility for Technical Engagements for any HW based verification project/engagement within EMEA. \nPresentation:  500M Gates in FPGAs (FPGA Prototyping) \nA few years ago the concept of running Billions of gates on an FGPA System would have been mind boggling. \nThis Cadence Presentation will offer an overview of the Protium™ Enterprise Prototyping Platform for fast hardware and software verification.\nWe will review the traditional prototyping challenges of complex SoCs using a 5G AI-enabled mobile SoC case study—RTL changes required for clock management\, memories\, interfaces\, multi-FPGA partitioning\, and multi-user support. \nYou will learn how the Protium X2 features and solutions solve these challenges while accelerating the hardware/software co-design verification schedule. \nRead MoreMyrtle Shah \nFounder\, Chipflow \nMyrtle is an engineer and founder at ChipFlow\, working on a reliable end-to-end open source flow for building chips. \n×Myrtle Shah\, Chipflow\nMyrtle is an engineer and founder at ChipFlow\, working on a reliable end-to-end open source flow for building chips. They are also the lead developer of nextpnr\, an open source FPGA place and route tool\, and the creator of the Project Trellis bitstream documentation and open flow for Lattice ECP5 FPGAs. They enjoy walking and gardening in their spare time when they need to get away from computers. \nPresentation:  OS RISC V SoC built with Python \nBy combining Amaranth\, a Python-based framework for describing and constructing hardware\, with a stack of other open source tools\, it’s possible to build complex SoCs not just for FPGAs but also taped out as chips. We’ll be having a look at the ecosystem for both as it stands today; some examples of projects using it including the journey to a tapeout-ready\, Linux-capable RISC-V SoC on the Skywater 130nm process; and what the future of open tooling might look like. \nRead More
URL:https://desn.org.uk/event/fpga-frontrunner-meet-greet/
CATEGORIES:Past Event
ATTACH;FMTTYPE=image/jpeg:https://desn.org.uk/wp-content/uploads/2022/01/NMIES-FPGA2.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20220317T120000
DTEND;TZID=Europe/London:20220317T190000
DTSTAMP:20220408T090730Z
CREATED:20220128T161320Z
LAST-MODIFIED:20220408T090730Z
UID:18153-1647518400-1647543600@desn.org.uk
SUMMARY:Technology Start-Up Event
DESCRIPTION:Technology Start-Up Event\nOur joint Silicon Catalyst and TechWorks event was conceived to help founders learn about the forming\, storming\, norming and then performing of UK semiconductor startup companies. \nWe had the great Malcolm Penn take us through the concept that no company is an island when testing their value proposition. \nWe kicked off with Phillip Burr describing the hugely generous Arm (a Silicon Catalyst strategic partner and In Kind Partner) Flexible Access program that releases the potential of semiconductor startup designers to get market leading design IP. \nTwo legends of our UK semiconductor startups Phil O’Donovan co-founder CSR Plc and Jerry Loraine talked about “how bad things happen to good people” with stories about patent trolls and go to market challenges. \nThis led naturally into “the importance of the team” with a single person invention idea from Bruno Johnson. Where Cascoda invented a radio architecture to increase range by 3x for Thread Group #iotdevices & is now shipping Arm based products into #smartcities #smartbuildings all around the world.\nThis section concluded with a compelling presentation from the illustrious Jim Nicholas walking us through the inventive team idea from Uniphy Ltd \nThe last session before the break had the wonderful Vaysh Kewada from Salience Labs (a Silicon Catalyst portfolio company) share her deep insights into “creating relentlessly repeatable processes from day 1” of your startup journey. Followed by a hugely insightful deep dive by Pete Hughes the foremost semiconductor product operations executive in the UK on how to ship high volume semiconductor products with the level of quality that your market leading customers will demand. \nBack from the break where the Arm catering team laid on a spread that would not look out of place at the Ritz\, we leapt into “what problem are you solving?” Patrick Camilleri shared his learnings on how to build semiconductor design IP combined SaaS product offerings and then Gary Spittle founder of Sonical Inc (A Silicon Catalyst portfolio company) projected the huge opportunity in their end to end system play to command the compute in the ear application space. \nWe concluded the presentations with the eternal “how much money will you need?” The marvellous Tony Milbourn who leads u-blox corporate venturing shared in detail how they look for the secret sauce of semiconductor startup success. Then Owen Metters Foresight Group Williams\, the leading semiconductor VC investor in the UK took us through three compelling case studies. \nThe final panel session lead us into a lively debate into what we need to do to make UK Semiconductor great again and make sure we create an open and inclusive industry where everybody can thrive.
URL:https://desn.org.uk/event/technology-start-up-event/
CATEGORIES:FREE for All,NMI Event,Past Event
ATTACH;FMTTYPE=image/gif:https://desn.org.uk/wp-content/uploads/2022/01/NMIESTSUE.gif
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20220309
DTEND;VALUE=DATE:20220310
DTSTAMP:20220728T125841Z
CREATED:20220218T133517Z
LAST-MODIFIED:20220728T125841Z
UID:18335-1646784000-1646870399@desn.org.uk
SUMMARY:Synopsys: Early and Accelerated SoC Connectivity Verification using VC Formal Connectivity Checking App
DESCRIPTION:Synopsys: Early and Accelerated SoC Connectivity Verification using VC Formal Connectivity Checking App\nRegisterComplex bus protocols\, increased on-chip functionalities\, coupled with limited shared I/O resources\, result in complex wiring connections in SoCs with numerous muxing schemes.\nSimulation and structural analysis approaches require huge effort and may lead to bug escapes making them inefficient for SoC connectivity verification. Connectivity verification using formal techniques is exhaustive and helps making designs immune to connectivity bug escapes. \nFor over a decade\, VC Formal Connectivity Checking App has become an essential part of the verification toolkit used by leading edge technology companies. Its ability to scale with the ever increasing SoC design sizes\, its performance and ease of use\, and its optimized debugging capabilities\, make it a market leader in this space. \nJoin us to learn about SoC connectivity challenges and how Synopsys’ innovative technologies can help you catch and debug sneaky wiring mistakes early with 100% confidence and ease.
URL:https://desn.org.uk/event/synopsys-early-and-accelerated-soc-connectivity-verification-using-vc-formal-connectivity-checking-app/
CATEGORIES:Past Event,Promoted Event
ATTACH;FMTTYPE=image/png:https://desn.org.uk/wp-content/uploads/2022/02/synweb2.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20220303T120000
DTEND;TZID=Europe/London:20220303T123000
DTSTAMP:20220408T091436Z
CREATED:20220207T153850Z
LAST-MODIFIED:20220408T091436Z
UID:18174-1646308800-1646310600@desn.org.uk
SUMMARY:Rules of Origin when exporting to the EU
DESCRIPTION:RULES OF ORIGIN WHEN EXPORTING TO THE EU\nRegister for FREEWhere your product comes from or is made\, can have a huge impact on the tariffs applicable when selling to another country. Ensuring your goods comply with the rules of origin in the EU/UK Trade & Cooperation Agreement is essential for you to export your product smoothly and avoid costly errors.\nAs of 1st January 2022\, to benefit from the reduced rate of Customs Duty\, all companies exporting goods to the EU must be able to prove that their goods are of UK/EU origin – it is no longer sufficient to make a declaration on your commercial invoice. Inability to do so may result in delays\, demands for duty and even penalties. \nThis essential one-hour webinar led by TechWorks and The International Trade Consultancy will cover: \n\nWhat are rules of origin?\nWhich rules of origin apply to my products?\nHow can I check if they comply?\nHow can I prove they comply?\nWhat should I do if they don’t comply?\nWhat is cumulation and does it apply to me?\n\nHosted by\nLucinda O’Reilly \nLucinda O’Reilly is an international trade consultant with over 10 years’ experience of global imports and exports. As the Exports Director of Ecotile Flooring she developed a successful UK focused manufacturing company to export to over 40 countries worldwide. Having successfully managed Ecotile’s transition through Brexit Lucinda set up The International Trade Consultancy to provide support to companies struggling to navigate the new regulatory landscape and supply chain challenges caused by the pandemic.
URL:https://desn.org.uk/event/rules-of-origin-when-exporting-to-the-eu/
CATEGORIES:NMI Event,Past Event
ATTACH;FMTTYPE=image/jpeg:https://desn.org.uk/wp-content/uploads/2022/02/webinarv2.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20220223T080000
DTEND;TZID=UTC:20220406T170000
DTSTAMP:20220728T131600Z
CREATED:20220217T192307Z
LAST-MODIFIED:20220728T131600Z
UID:18334-1645603200-1649264400@desn.org.uk
SUMMARY:Cadence TECHTALK Series: Adopting a Faster\, More Efficient Path to Multi-Chiplet Design
DESCRIPTION:Cadence TECHTALK Series: Adopting a Faster\, More Efficient Path to Multi-Chiplet Design\nRegisterWith the increasing popularity of multi-chiplet designs that address Moore’s law slowdown and reticle size limitations\, leading foundries are offering multiple advanced packaging and die stacking options for different applications.\nEDA companies have had to innovate to provide integrated and IC-centric tools while building accurate system-level models to find the fastest and most efficient path for 3D-IC design and analysis. \nIn this four-part CadenceTECHTALK series\, learn how to properly plan and implement stacked digital SoCs\, analog/mixed-signal designs\, and entire 2.5-D/3-D systems\, including meeting system-level power and thermal analysis requirements through an integrated 3D-IC solution.
URL:https://desn.org.uk/event/cadence-techtalk-series-adopting-a-faster-more-efficient-path-to-multi-chiplet-design/
CATEGORIES:Past Event
ATTACH;FMTTYPE=image/jpeg:https://desn.org.uk/wp-content/uploads/2022/02/cad3.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20220217T120000
DTEND;TZID=Europe/London:20220217T123000
DTSTAMP:20220408T092109Z
CREATED:20220207T154453Z
LAST-MODIFIED:20220408T092109Z
UID:18164-1645099200-1645101000@desn.org.uk
SUMMARY:Commodity Codes and Import Declarations
DESCRIPTION:COMMODITY CODES AND IMPORT DECLARATIONS\nRegister for FREEOn January 1st 2022\, two changes came into effect that importers and exporters should be aware of. The World Customs Organisation updated the Harmonised System so there have been a number of changes to commodity codes\, especially for electronic products.\nFull import declarations are now required for all goods entering GB from the EU at point of import and a new digital system is in place to manage the increase in data. \nThis essential 30 minute webinar led by TechWorks and The International Trade Consultancy will cover: \n\nWhat are commodity codes?\nHow can I check my commodity codes are still correct?\nWhat do I need to do if they’ve changed?\nHow does the new import declaration system work?\nHow will it affect my business?\n\nHosted by\nLucinda O’Reilly \nLucinda O’Reilly is an international trade consultant with over 10 years’ experience of global imports and exports. As the Exports Director of Ecotile Flooring she developed a successful UK focused manufacturing company to export to over 40 countries worldwide. Having successfully managed Ecotile’s transition through Brexit Lucinda set up The International Trade Consultancy to provide support to companies struggling to navigate the new regulatory landscape and supply chain challenges caused by the pandemic.
URL:https://desn.org.uk/event/commodity-codes-and-import-declarations/
CATEGORIES:NMI Event,Past Event
ATTACH;FMTTYPE=image/jpeg:https://desn.org.uk/wp-content/uploads/2022/02/webinarsv1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20220210T180000
DTEND;TZID=Europe/London:20220210T190000
DTSTAMP:20220408T091929Z
CREATED:20220121T134734Z
LAST-MODIFIED:20220408T091929Z
UID:18107-1644516000-1644519600@desn.org.uk
SUMMARY:Synopsys: 3DIC Design from Concept to Silicon
DESCRIPTION:Synopsys: 3DIC Design from Concept to Silicon\nREGISTERFor some high-performance computing (HPC) designs\, monolithic SoCs aren’t producing the scalability and yield that designers are looking for. New trends towards 3DIC design are emerging introducing new design challenges\, such as reliable die-to-die connectivity\, high bandwidth memory\, integration\, and 2.5D or 3D packaging options. This webinar will outline the different market trends for 3DIC designs and explain how designers can maintain such new trends to deliver their designs with optimized latency\, power\, performance\, and area. We will also demonstrate the construction of a 3DIC design and our 3rd generation HBM interposer auto-routing solution. \nAttendees will: \n\nLearn about considerations and trends for a more efficient 3DIC design integration\nFind out how protocols like HBM3 and Die-to-Die are influencing 3DIC designs\nSee a demo of a 3DIC design construction\n\nSPEAKERS\nKenneth Larsen is a product marketing director in the Silicon Realization Group at Synopsys. He is a versatile leader with a strong background in defining and executing product vision\, marketing strategy\, inspiring product development teams\, translating technology concepts into customer solutions\, developing high-performance global organizations\, conceiving and driving new and emerging products to scale from the ground up\, guiding marketing\, and enabling sales. Kenneth has a degree in electrical engineering and additional coursework in strategic growth at Columbia Business School\, and Artificial Intelligence at MIT Sloan School of Management. \nEric Means is an Applications Engineer in Hillsboro\, Oregon supporting Synopsys 3DIC Compiler users. He has worked with ASIC and EDA customers for 25 years at NEC\, Renesas\, & Synopsys. He has a BS in Electrical Engineering from Washington State University and an MS in Computer Engineering from the Oregon Graduate Institute. \n*This webinar is in partnership with SemiWiki and Synopsys*
URL:https://desn.org.uk/event/synopsys-3dic-design-from-concept-to-silicon/
CATEGORIES:Past Event,Promoted Event
ATTACH;FMTTYPE=image/jpeg:https://desn.org.uk/wp-content/uploads/2022/01/3DIC-Design-from-Concept-to-Silicon-Max-Quality.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20220209T173000
DTEND;TZID=Europe/London:20220209T180000
DTSTAMP:20220728T130826Z
CREATED:20220121T135503Z
LAST-MODIFIED:20220728T130826Z
UID:18110-1644427800-1644429600@desn.org.uk
SUMMARY:Synopsys: Exploring a Software First Approach to Avoid SoC Re-spins
DESCRIPTION:Synopsys: Exploring a Software First Approach to Avoid SoC Re-spins\nREGISTERTraditional coverage-based verification methods are no longer sufficient to verify complex SoCs integrating many processor cores and IP subsystems.  To conquer the verification challenge of complex SoCs\, companies are shifting their development paradigm to a software first approach.  By considering the target software up front\, as a critical part of the SoC development process\, designs teams are able to signoff a new SoC for production with high confidence. \nIn this Synopsys webinar we will cover the primary pre-silicon methods\, along with their benefits\, to execute a software first strategy: \n– Virtual prototyping\n– Emulation\n– FPGA-based prototyping \nThrough the example of a production processor design project\, we will provide insight into each methodology and how it helps to accelerate verification coverage.  This event is hosted by a software first methodology expert and aimed at verification and software teams working on next-generation SoC designs.
URL:https://desn.org.uk/event/synopsys-exploring-a-software-first-approach-to-avoid-soc-re-spins/
CATEGORIES:Past Event
ATTACH;FMTTYPE=image/png:https://desn.org.uk/wp-content/uploads/2022/02/synweb2.png
END:VEVENT
END:VCALENDAR