BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//DESN - ECPv6.17.3//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-WR-CALNAME:DESN
X-ORIGINAL-URL:https://desn.org.uk
X-WR-CALDESC:Events for DESN
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:Europe/London
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20220327T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20221030T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20230326T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20231029T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20240331T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20241027T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20231127T100000
DTEND;TZID=Europe/London:20231127T143000
DTSTAMP:20231116T131547Z
CREATED:20231106T171449Z
LAST-MODIFIED:20231116T131547Z
UID:19282-1701079200-1701095400@desn.org.uk
SUMMARY:FPGA Frontrunner Meet and Greet
DESCRIPTION:FPGA Frontrunner Meet & Greet\nSecurity at System Level\, and what security features we need in our FPGA to support this\nRegisterThe FPGA Front Runners event will be hosted by Thales at their venue in Reading.\nThe event will focus on “Security at System Level\, and what security features we need in our FPGA to support this”. \nIf you are interested in speaking at this event please email mike.bartley@techworks.org.uk \nTopics for talks: \n\nWhat is Security in FPGA-based Systems?\nWhat security features do we need our FPGAs to support this?\nExample applications and the implications for security\n(this is NOT supply-chain security)\n\nAgenda:  \n\n\n\n10:00\nRegistration\, arrival and refreshments\n\n\n10.30\nPeter Davies\, Thales – “Security in FPGA-based Systems”\n\n\n11:00\nMark Frost\, Intel – “Security in FPGA”\n\n\n11:20\nIan Pearson\, Microchip – “System and Device Level Security Considerations”\n\n\n11:40\nMaximilian Werner\, Efinix Inc – “Efinix FPGA Encryption solution”\n\n\n12:00\nFabio Caccamo & Chris Palmer from AMD\n\n\n12:30\nSimon Bowles\, Product Cyber Security Specialist\, Rolls Royce –  “RR’s product security goals and the context in which we use FPGAs”\n\n\n12:45\nAnkith Srinivasan\, Cirrus Rays Pvt Ltd  – “Physically Unclonable Functions (PUFs) in FPGA security”\n\n\n13:00\nWorking lunch in small groups – “FPGA use models and possible security concerns”\n\n\n14:00\nPresentations by each group\n\n\n14:30\nFinish refreshments/networking\n\n\n\n\nRegistration on the day via Thales’s front desk\nParking available – car registration needed
URL:https://desn.org.uk/event/fpga-frontrunner-meet-and-greet-3/
LOCATION:Thales\, 350 Longwater Ave\, Reading\, RG2 6GF\, United Kingdom
CATEGORIES:FREE for Members
ATTACH;FMTTYPE=image/jpeg:https://desn.org.uk/wp-content/uploads/2023/11/DESN-FPGA-November-23.jpg
END:VEVENT
END:VCALENDAR