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BEGIN:VEVENT
DTSTART;VALUE=DATE:20260623
DTEND;VALUE=DATE:20260624
DTSTAMP:20260511T083050Z
CREATED:20260414T123406Z
LAST-MODIFIED:20260511T083050Z
UID:23540-1782172800-1782259199@desn.org.uk
SUMMARY:Verification & Semiconductors Futures Conference UK 2026
DESCRIPTION:Verification Futures UK 2026\, co-located with Semiconductors Futures 2026 co-organised by Tessolve and Alpinum.\nThe conference continues its strong tradition of delivering a unique blend of conference presentations\, exhibitions\, training\, and industry networking sessions focused on the challenges faced in hardware and software verification. The event remains an important forum for end-users to define their verification challenges and collaborate with engineers\, researchers\, and vendors to shape practical solutions. In 2026\, Verification Futures continues to strengthen its core emphasis on verification methodologies\, DV tools\, and engineering workflows\, including areas such as formal methods for complex SoCs\, CPU & RISC-V verification\, open-source and licence-free verification tools\, AI in design verification (AI in DV)\, verification planning and coverage\, and HW/SW co-verification. \nSemiconductors Futures 2026 brings together the semiconductor community\, covering AI/ML in IP & SoC design\, AI’s impact on EDA and workflows\, FPGA & mixed-signal\, with a focus on the automotive\, data centre\, and AI products. New tracks consider emerging technologies such as quantum computing\, photonics\, and chiplets\, as well as startups and investments. We expect 50+ engineering students to attend a separate session. \nDetailsSimon Southwell\nSystems Consultant\nWyvern Semiconductors \n×Simon Southwell\nComplex protocol modelling with OSVVM co-simulation\, exploring the PCIe VC \nA look at OSVVM co-simulation features and their use for constructing complex protocol verification component using PCIe as an example. It looks at the integration of the PCIe GEN1/GEN2 C model from the presenter’s pcieVHost project\, using OSVVM’s co-simulation capabilities\, to construct an OSVVM compatible Verification Component (VC)\, used like any other VHDL based VC\, but with additional features\, to drive 3rd party PCIe IP. An example of driving Altera’s Cyclone V Hard IP for PCI Express is discussed. \nBiography \nEngineer with 35+ years in R&D\, with experience in ASIC design\, FPGA\, and embedded software development. Currently working on developing open-source IP in areas such as co-simulation and system modelling. A collaborator on the OSVVM project\, adding and supporting its co-simulation capabilities and developing verification IP. \nAreas of experiences include logic IP for both ASIC and FPGA\, logic verification\, HPC\, processor systems\, networking (802.3 and proprietary)\, embedded software\, co-simulation technology\, software modelling of SoC systems\, data compression logic\, PCIe endpoint design\, cellular (3G and 4G)\, wireless (802.11 and 802.15.4). Joint or sole author on several logic IP related patents. \nDetailsRojalin Mishra\nLead Verification Engineer\nRiver Lane \n×Rojalin Mishra\nFrom Qubits to Confidence: Verifying Quantum Error Correction \nQuantum error correction (QEC) introduces fundamentally new challenges for verification\, where probabilistic behaviour and correlated errors break many conventional methodologies. This talk explores how we adapt verification strategies to this domain\, including designing testbenches for probabilistic measurement data\, modelling spatially and temporally correlated noise\, and defining meaningful coverage for error correction circuits. \nThrough real debugging case studies\, we highlight subtle failure modes unique to quantum systems—such as silent corruption during syndrome extraction—and discuss approaches to validating decoder behaviour across complex syndrome spaces. We also examine how verification can be performed under realistic noise distributions to build confidence in system-level reliability. \nBio: I am an Electronics and Communications engineer with over a decade of experience in ASIC/FPGA verification\, specialising in complex digital systems and verification methodologies. I currently serve as a Lead Verification Engineer\, driving UVM-based verification for Quantum Error Correction within the rapidly evolving field of Quantum Computing. \nDetailsSteinn Gustafsson\nFounder\nChevin Technology \n×Steinn Gustafsson\nPresentation Title: Complex protocol modelling with OSVVM co-simulation\, exploring the PCIe VC \nA look at OSVVM co-simulation features and their use for constructing complex protocol verification component using PCIe as an example. It looks at the integration of the PCIe GEN1/GEN2 C model from the presenter’s pcieVHost project\, using OSVVM’s co-simulation capabilities\, to construct an OSVVM compatible Verification Component (VC)\, used like any other VHDL based VC\, but with additional features\, to drive 3rd party PCIe IP. An example of driving Altera’s Cyclone V Hard IP for PCI Express is discussed. \nBio: Engineer with 35+ years in R&D\, with experience in ASIC design\, FPGA\, and embedded software development. Currently working on developing open-source IP in areas such as co-simulation and system modelling. A collaborator on the OSVVM project\, adding and supporting its co-simulation capabilities and developing verification IP. \nAreas of experiences include logic IP for both ASIC and FPGA\, logic verification\, HPC\, processor systems\, networking (802.3 and proprietary)\, embedded software\, co-simulation technology\, software modelling of SoC systems\, data compression logic\, PCIe endpoint design\, cellular (3G and 4G)\, wireless (802.11 and 802.15.4). Joint or sole author on several logic IP related patents. \nDetailsYassine Eben Aimine\nSiemens \n×Yassine Eben Aimine\nYassine has more than 20 years’ experience in the EDA industry. Throughout his professional career\, Yassine has partnered with design and verification engineers to deploy the latest technologies in EDA tooling in the areas of design for test\, functional verification\, and functional safety. \nDetailsPhill J Payne\nPrincipal Digital Design Engineer\nNovomorphic \n×Phill J Payne\nPhill J Payne is Principal Digital Design Engineer at Novomorphic\, specialising in secure\, real-time FPGA and embedded architectures for edge AI. He is developing convolution acceleration and a modular hardware fabric that composes reconfigurable pipelines\, reduces memory pressure\, and delivers high-performance vision and inference at the edge. Across 26 years\, Phill has turned novel architectural ideas into deployable systems under tight power\, latency\, throughput\, and reliability constraints\, with deep experience in security-grade FPGA development and signal-processing workloads. Previously\, he delivered end-to-end FPGA firmware and software for advanced systems\, including a patented communications technique designed to operate in contested jamming environments\, later acquired by a major defence prime. He also built specialised training systems used in preparation for the London 2012 Olympic Games\, translating complex engineering into practical tools. \nDetailsGavin Lofts\nField Applications Engineer\nAltera \n×Gavin Lofts\nGavin Lofts is a Field Applications Engineer at Altera with 20+ years of experience in hardware\, embedded software\, and FPGA design. He has worked on systems ranging from biosensors to radio. \nPresentation: CI/CD and Git for Modern FPGA Development
URL:https://desn.org.uk/event/verification-semiconductors-futures-conference-uk-2026/
LOCATION:University of Reading\, Whiteknights PO Box 217\, Reading\, Berkshire\, RG6 6AH\, United Kingdom
CATEGORIES:DESN Event,DESN Promoted Event
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END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260614
DTEND;VALUE=DATE:20260618
DTSTAMP:20260428T171041Z
CREATED:20260428T170947Z
LAST-MODIFIED:20260428T171041Z
UID:23586-1781395200-1781740799@desn.org.uk
SUMMARY:29th World Micromachining Summit
DESCRIPTION:
URL:https://mms2026.soton.ac.uk/#new_tab
LOCATION:Southampton
CATEGORIES:DESN Promoted Event
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END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260326
DTEND;VALUE=DATE:20260327
DTSTAMP:20260204T141801Z
CREATED:20260204T141718Z
LAST-MODIFIED:20260204T141801Z
UID:23298-1774483200-1774569599@desn.org.uk
SUMMARY:IMAPS-UK: MicroTech 2026 Conference
DESCRIPTION:IMAPS-UK: MicroTech 2026 ConferenceREGISTERIMAPS-UK: MicroTech 2026 Conference at King’s Conference Centre\, Hedge End\, Southampton – Thursday 26th March 2026 and Heterogeneous Integration – Explained! Workshop at University of Southampton on Wednesday 25 March 2026 \nThe IMAPS-UK MicroTech 2026 Conference on Thursday 26th March 2026 at the King’s Conference Centre\, Hedge End\, Southampton will focus on Driving Innovation in Semiconductor Packaging. The preliminary Conference Agenda includes state-of-the-art presentations on the advanced packaging market\, the UK Semiconductor Centre\, advanced packaging technologies including laser based processes\, heterogeneous integration\, interposers and 3D integration. \nMore Information and Registration: https://www.imaps.org.uk/events/microtech-2026-driving-innovation-in-semiconductor-packaging/ \nThe Conference is complemented by a Workshop on Heterogeneous Integration – Explained! On Wednesday 25th March 2026 at the University of Southampton. \nMore Information and Registration: https://www.imaps.org.uk/events/heterogeneous-integration-electronics/ \nPlease contact the IMAPS-UK Office (office@imaps.org.uk ) with any questions.
URL:https://desn.org.uk/event/imaps-uk-microtech-2026-conference/
LOCATION:Southampton
CATEGORIES:DESN Promoted Event
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BEGIN:VEVENT
DTSTART;TZID=Europe/London:20250717T163000
DTEND;TZID=Europe/London:20250717T190000
DTSTAMP:20250624T130321Z
CREATED:20250624T130105Z
LAST-MODIFIED:20250624T130321Z
UID:22924-1752769800-1752778800@desn.org.uk
SUMMARY:Innovating for Investment: Harnessing Innovation and IP to Drive Growth
DESCRIPTION:
URL:https://eip.com/uk/latest/events/innovating-for-investment-how-the-right-approach-to-innovation-and-ip-can-help-grow-and-secure-investment#new_tab
LOCATION:Bradford\, CB4 0GA
CATEGORIES:DESN Promoted Event
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END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20230914
DTEND;VALUE=DATE:20230915
DTSTAMP:20230728T084703Z
CREATED:20230714T094232Z
LAST-MODIFIED:20230728T084703Z
UID:19254-1694649600-1694735999@desn.org.uk
SUMMARY:Tessolve: Verification Futures
DESCRIPTION:Verification Futures\nRegisterThe conference is focused on hardware design verification.\nThe full conference program includes 17 talks covering verification challenges and solutions\, formal verification\, RISC-V\, System Verilog\, UVM for AMS Verification\, and VHDL Verification \nFull conference agenda below \n08:30 Arrival: Breakfast and Networking\n09:25 Welcome: Mike Bartley\, Tessolve Semiconductor Ltd\n09:30 Safety and Security challenges in hardware IP development\, Vivek Vedula\, ARM Ltd\n10:15 Ericsson’s Challenges of IP Development and Verification for Products with a Long Shelf Life\, Alex Duhovich\, Ericsson\n10:30 Cadence\n11:00 Refreshments and Networking\n11:30 Parallel tracks\n11:30 10 years of Verification Challenges Mike Bartley\, Tessolve\nRISCV CPU Verification – Opportunities and Challenges\, Divyang Agrawal\, Tenstorrent\, Inc\nValidation of Hybrid Architectures\, Suneil Mohan\, Intel Corporation\n11.30 What Can Formal Do For Me? Doug Smith\, Doulos\n11.30 Renesas’s Submission to the UVM-(A)MS working group\, Peter Grove & Steven Holloway\, Renesas\n12:30 Lunch and Networking\n13:30 A Modern Fable: The Lost Art of Processor Verification\, Larry Lapides (Imperas Software Ltd\n14:00 Advanced RISC-V Verification Technique Learnings for SoC Validation\, David Kelf\, Breker Verification System\n14:20 Improve the Quality of the Testbenches using specialized PySlint solutions\, Balram Naik Meghavath\, Broadcom ltd\n14:40 Hemendra Talesara\n15:00 Refreshments and Networking\n15:30 Parallel tracks\n15:30 Leveraging AMS verification and DMS verification for efficiency and quality in Mixed-signal designs\, Aditya Devarakonda\, NXP Semiconductor\nSigmasense\nMethodology focused testbench generation\, Benjamin Delsol – UVMGEN\n15:30 Using Non-Determinism with Formal? Doug Smith\, Doulos\n15:30 Faster than “Lite” Verification Component Development with OSVVM\, Jim Lewis\, SynthWorks Design Inc \nRegister now\nhttps://www.tessolve.com/verification-futures/vf2023-us/
URL:https://desn.org.uk/event/tessolve-verification-futures/
LOCATION:Austin\, Austin\, Texas
CATEGORIES:DESN Promoted Event
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BEGIN:VEVENT
DTSTART;VALUE=DATE:20230911
DTEND;VALUE=DATE:20230915
DTSTAMP:20230222T163325Z
CREATED:20230222T162920Z
LAST-MODIFIED:20230222T163325Z
UID:19124-1694390400-1694735999@desn.org.uk
SUMMARY:IMAPS-UK: EMPC23 - The 24th European Microelectronics & Packaging Conference
DESCRIPTION:IMAPS-UK: EMPC23 – The 24th European Microelectronics & Packaging Conference\nRegisterThe 24th European Microelectronics Packaging Conference (EMPC 2023) will return to the United Kingdom after 12 years and will be hosted at the Genome Centre in Hinxton\, near Cambridge from 11 – 14th September 2023. The website provides some initial information on the Conference\, including: \n\nProgramme Themes\nCall for Abstracts Timetable\nConference Schedule\nExhibition and Sponsorship\nThe Venue – Genome Centre\nTravel and Accommodation\n\nYou will attend presentations and posters from leading companies and academic institutions on emerging trends in electronics devices and associated technology. The event will introduce new materials and opportunities in the packaging of electronic devices and potential applications of systems. We are planning that EMPC 2023 will be run as a face to face event\, enabling attendees and exhibitors to network personally in the spacious surrounds of the Genome Centre. \nFind out more
URL:https://desn.org.uk/event/imaps-uk-empc23-the-24th-european-microelectronics-packaging-conference/
LOCATION:Genome Centre\, Hinxton\, Cambridgeshire
CATEGORIES:DESN Promoted Event
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END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20230704
DTEND;VALUE=DATE:20230706
DTSTAMP:20230222T130018Z
CREATED:20230222T125913Z
LAST-MODIFIED:20230222T130018Z
UID:19120-1688428800-1688601599@desn.org.uk
SUMMARY:IMAPS-UK: CPE2023 – Centre for Power Electronics Annual Conference
DESCRIPTION:IMAPS-UK: CPE2023 – Centre for Power Electronics Annual Conference\nRegisterThe Centre for Power Electronics (CPE) Annual Conference will bring together the Power Electronics\, Machines and Drives Community to review the latest Research and Development that will impact the Electric Revolution.\nThis Conference will feature Invited Keynotes and Presentations from Leading Academics and Industrialists\, views of the Future Demands for Power Electronics and Drives and hearing about the latest research advances from the Centre for Doctoral Training in Sustainable Electric Propulsion and other Post Graduates and Post Doctoral Researchers. \nThe Conference will be run over 2 days to provide a comprehensive review of status of Power Electronics Research and Development\, including topics selected from: \n\nSemiconductor and Passive Devices\nPackaging and Interconnection\nConverters and Drives\nControl\, Test and Reliability\n\nPower Electronics and Drives Related Applications \nThe Conference will be preceded by a Workshop on Power Electronics Devices and Packaging – Training and Upskilling at the same venue on Monday 3 July 2023\, where attendees at the CPE 2023 Conference will receive a discounted rate. \nFind out more
URL:https://desn.org.uk/event/imaps-uk-cpe2023-centre-for-power-electronics-annual-conference/
LOCATION:University of Nottingham\, Jubilee Conference Centre\, Nottingham
CATEGORIES:DESN Promoted Event
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BEGIN:VEVENT
DTSTART;TZID=Europe/London:20230330T083000
DTEND;TZID=Europe/London:20230330T160000
DTSTAMP:20230222T125205Z
CREATED:20230222T122428Z
LAST-MODIFIED:20230222T125205Z
UID:19110-1680165000-1680192000@desn.org.uk
SUMMARY:IMAPS-UK: Microtech 2023 – Advanced Packaging and Technology Trends
DESCRIPTION:IMAPS-UK: Microtech 2023 – Advanced Packaging and Technology Trends\nRegisterMicroTech 2023 will be an In Person Event on Thursday 30th March 2023 at University of Strathclyde Technology & Innovation Centre\, 99 George Street\, Glasgow\, G1 1RD\nMicroTech 2023 is the Annual IMAPS-UK Conference which will focus on Advanced Packaging and Technology Trends. This In Person Conference combines invited Keynotes and presentations from leading Industrial Companies and Research Institutions. The Conference will also include the IMAPS-UK Annual General Meeting (AGM). \nMicroTech 2023 will address the themes such as market analysis including current and future supply chain requirements\, providing examples of the implementation of advanced packaging technologies in challenging applications\, the development of sustainable materials and processes and latest advances in the assessment of quality and reliability. Advanced Packaging Technologies will not only be expected to demonstrate enhanced performance at the best possible cost\, but also improved efficiency\, reduced thermal impact and overall life cycle cost benefits. \nFind out more
URL:https://desn.org.uk/event/microtech-2023-advanced-packaging-and-technology-trends/
LOCATION:University of Strathclyde – Technology & Innovation Centre\, 99 George Street\, Glasgow\, G1 1RD
CATEGORIES:DESN Promoted Event
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END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20230321T130000
DTEND;TZID=Europe/London:20230321T140000
DTSTAMP:20230308T095153Z
CREATED:20230308T095123Z
LAST-MODIFIED:20230308T095153Z
UID:19136-1679403600-1679407200@desn.org.uk
SUMMARY:ZEISS: Quick methods for examination of p/n junctions in power devices webinar
DESCRIPTION:ZEISS: Quick methods for examination of p/n junctions in power devices webinar\nRegisterPower semiconductors are key components for transportation\, electrical grids\, and industrial drives. As the reliability of such devices can be affected by such phenomena as overcurrent\, desaturation\, and avalanche breakdown\, it is critical to be able to evaluate junction health and uniformity with simple methods. This webinar will demonstrate the value of analysing power semiconductors in FA with Passive Voltage Contrast (PVC) in the SEM as well as nanoprobing concepts such as Electron Beam Induced Current (EBIC). These techniques in combination examine not only the metallurgical p/n junction but also the corresponding depletion zones of the junction. An experimental method for examining the depletion zones in-situ as the gate bias will also be presented. \nFind out more
URL:https://desn.org.uk/event/zeiss-quick-methods-for-examination-of-p-n-junctions-in-power-devices-webinar/
LOCATION:Webinar
CATEGORIES:DESN Promoted Event
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BEGIN:VEVENT
DTSTART;VALUE=DATE:20220705
DTEND;VALUE=DATE:20220707
DTSTAMP:20220408T141745Z
CREATED:20220408T114721Z
LAST-MODIFIED:20220408T141745Z
UID:18734-1656979200-1657151999@desn.org.uk
SUMMARY:IMAPS-UK Event: Centre for Power Electronics Annual Conference
DESCRIPTION:IMAPS-UK Event: Centre for Power Electronics Annual Conference\nRegisterThe Centre for Power Electronics (CPE) Annual Conference will bring together the Power Electronics\, Machines and Drives Community to review the latest Research and Development that will impact the Electric Revolution. \nThe attendees are offered exceptional value at attractive prices to participate in the Conference with support from the Centre for Power Electronics (www.powerelectronics.ac.uk)\, focusing on encouraging Students and Early Career Researchers to demonstrate their ideas and network with the PEMD community.
URL:https://desn.org.uk/event/imaps-uk-event-centre-for-power-electronics-annual-conference/
LOCATION:University of Warwick\, Gibbet Hill Road\, Coventry\, CV4 7AL\, United Kingdom
CATEGORIES:DESN Promoted Event
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END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20220616
DTEND;VALUE=DATE:20220617
DTSTAMP:20220408T115507Z
CREATED:20220408T115157Z
LAST-MODIFIED:20220408T115507Z
UID:18744-1655337600-1655423999@desn.org.uk
SUMMARY:IMAPS-UK Event: PEPTUS Training Workshop
DESCRIPTION:IMAPS-UK Event: PEPTUS Training Workshop\nRegisterIMAPS-UK is organising a full-day Power Electronics Packaging Training Workshop to provide a basic understanding of the design\, testing and reliability issues involved in the assembly of power electronics components and modules that will form the basis of the Electric Revolution. \nThis workshop will focus on the fundamental aspects of power electronics packaging\, explaining the design considerations\, exploring the testing and reliability aspects and introducing the trends towards advanced packaging. This workshop will be complemented with a tour of the facilities at the CSA Catapult.
URL:https://desn.org.uk/event/imaps-uk-event-peptus-training-workshop/
LOCATION:CSA Catapult\, Innovation Centre\, Newport\, Duffryn\, NP10 8UL\, United Kingdom
CATEGORIES:DESN Promoted Event
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END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20220519
DTEND;VALUE=DATE:20220520
DTSTAMP:20220419T095323Z
CREATED:20220419T094540Z
LAST-MODIFIED:20220419T095323Z
UID:18759-1652918400-1653004799@desn.org.uk
SUMMARY:ECS: The Electronic Component Show
DESCRIPTION:ECS: The Electronic Component Show\nRegisterThis new one-day event offers the opportunity for design engineers and purchasing professionals to network with electronic manufacturers\, distributors and service providers to source new products\, solutions and contacts. \nECS is a one day table top event that has been launched for those who design\, source and buy electronic components & associated services. \nOrganised by MMG Publishing\, publisher of Electronics Sourcing and eBOM. com\, the event aims to bring together the industry’s leading manufacturers and distributors with design engineers and purchasing professionals. \nOffering an informative dual seminar program\, this one day event is the place where ideas will be shared\, meaningful conversations will be had and business relationships can start or be strengthened. \nTo be held on Thursday 19th May 2022 at the Kassam Stadium (Oxford United FC) in Oxford; this central location is easily accessible with ample free car parking and local train stations.
URL:https://desn.org.uk/event/ecs-the-electronic-component-show/
LOCATION:Kassam Stadium\, Littlemore\, Oxford\, OX4 6DE
CATEGORIES:DESN Promoted Event
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END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20220510T091500
DTEND;TZID=UTC:20220510T170000
DTSTAMP:20220411T151724Z
CREATED:20220411T151724Z
LAST-MODIFIED:20220411T151724Z
UID:18751-1652174100-1652202000@desn.org.uk
SUMMARY:Raising Partners Live: Funding in Focus 2022
DESCRIPTION:Raising Partners Live: Funding in Focus 2022\nRegisterRaising Partners Live is hosting this full day event at the Technology & Innovation Centre\, University of Strathclyde\, Glasgow\, bringing together investors and entrepreneurs to advance the entrepreneurial ecosystem by empowering start-up and scale-up tech business to access capital. \nThe one-day conference will focus on everything you need to know about raising investment. Hear from an array of world-class speakers\, participate in practical workshops\, meet investors\, and pitch your business to the professionals. \n Limited free tickets available: Raising Partners Live – Raising Partners Live 2022
URL:https://desn.org.uk/event/raising-partners-live-funding-in-focus-2022/
LOCATION:University of Strathclyde\, 16 Richmond Street\, Glasgow\, G1 1XQ
CATEGORIES:DESN Promoted Event
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END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20220426
DTEND;VALUE=DATE:20220427
DTSTAMP:20220408T093743Z
CREATED:20220408T090018Z
LAST-MODIFIED:20220408T093743Z
UID:18635-1650931200-1651017599@desn.org.uk
SUMMARY:CadenceTECHTALK: Accelerating Complex SoC Prototyping with Protium X2
DESCRIPTION:CadenceTECHTALK: Accelerating Complex SoC Prototyping with Protium X2\nRegisterThis CadenceTECHTALK will offer an overview of the Protium™ Enterprise Prototyping Platform for fast hardware and software verification.\nWe will review the traditional prototyping challenges of complex SoCs using a 5G AI-enabled mobile SoC case study—RTL changes required for clocks management\, memories\, interfaces\, multi-FPGA partitioning\, and multi-user support. Learn how the Protium X2 platform features and solutions solve these challenges while accelerating the hardware/software co-design verification schedule.
URL:https://desn.org.uk/event/cadencetechtalk-accelerating-complex-soc-prototyping-with-protium-x2/
LOCATION:Webinar
CATEGORIES:DESN Promoted Event
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END:VCALENDAR