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DTSTART;VALUE=DATE:20260623
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UID:23540-1782172800-1782259199@desn.org.uk
SUMMARY:Verification & Semiconductors Futures Conference UK 2026
DESCRIPTION:Verification Futures UK 2026\, co-located with Semiconductors Futures 2026 co-organised by Tessolve and Alpinum.\nThe conference continues its strong tradition of delivering a unique blend of conference presentations\, exhibitions\, training\, and industry networking sessions focused on the challenges faced in hardware and software verification. The event remains an important forum for end-users to define their verification challenges and collaborate with engineers\, researchers\, and vendors to shape practical solutions. In 2026\, Verification Futures continues to strengthen its core emphasis on verification methodologies\, DV tools\, and engineering workflows\, including areas such as formal methods for complex SoCs\, CPU & RISC-V verification\, open-source and licence-free verification tools\, AI in design verification (AI in DV)\, verification planning and coverage\, and HW/SW co-verification. \nSemiconductors Futures 2026 brings together the semiconductor community\, covering AI/ML in IP & SoC design\, AI’s impact on EDA and workflows\, FPGA & mixed-signal\, with a focus on the automotive\, data centre\, and AI products. New tracks consider emerging technologies such as quantum computing\, photonics\, and chiplets\, as well as startups and investments. We expect 50+ engineering students to attend a separate session. \nDetailsSimon Southwell\nSystems Consultant\nWyvern Semiconductors \n×Simon Southwell\nComplex protocol modelling with OSVVM co-simulation\, exploring the PCIe VC \nA look at OSVVM co-simulation features and their use for constructing complex protocol verification component using PCIe as an example. It looks at the integration of the PCIe GEN1/GEN2 C model from the presenter’s pcieVHost project\, using OSVVM’s co-simulation capabilities\, to construct an OSVVM compatible Verification Component (VC)\, used like any other VHDL based VC\, but with additional features\, to drive 3rd party PCIe IP. An example of driving Altera’s Cyclone V Hard IP for PCI Express is discussed. \nBiography \nEngineer with 35+ years in R&D\, with experience in ASIC design\, FPGA\, and embedded software development. Currently working on developing open-source IP in areas such as co-simulation and system modelling. A collaborator on the OSVVM project\, adding and supporting its co-simulation capabilities and developing verification IP. \nAreas of experiences include logic IP for both ASIC and FPGA\, logic verification\, HPC\, processor systems\, networking (802.3 and proprietary)\, embedded software\, co-simulation technology\, software modelling of SoC systems\, data compression logic\, PCIe endpoint design\, cellular (3G and 4G)\, wireless (802.11 and 802.15.4). Joint or sole author on several logic IP related patents. \nDetailsRojalin Mishra\nLead Verification Engineer\nRiver Lane \n×Rojalin Mishra\nFrom Qubits to Confidence: Verifying Quantum Error Correction \nQuantum error correction (QEC) introduces fundamentally new challenges for verification\, where probabilistic behaviour and correlated errors break many conventional methodologies. This talk explores how we adapt verification strategies to this domain\, including designing testbenches for probabilistic measurement data\, modelling spatially and temporally correlated noise\, and defining meaningful coverage for error correction circuits. \nThrough real debugging case studies\, we highlight subtle failure modes unique to quantum systems—such as silent corruption during syndrome extraction—and discuss approaches to validating decoder behaviour across complex syndrome spaces. We also examine how verification can be performed under realistic noise distributions to build confidence in system-level reliability. \nBio: I am an Electronics and Communications engineer with over a decade of experience in ASIC/FPGA verification\, specialising in complex digital systems and verification methodologies. I currently serve as a Lead Verification Engineer\, driving UVM-based verification for Quantum Error Correction within the rapidly evolving field of Quantum Computing. \nDetailsSteinn Gustafsson\nFounder\nChevin Technology \n×Steinn Gustafsson\nPresentation Title: Complex protocol modelling with OSVVM co-simulation\, exploring the PCIe VC \nA look at OSVVM co-simulation features and their use for constructing complex protocol verification component using PCIe as an example. It looks at the integration of the PCIe GEN1/GEN2 C model from the presenter’s pcieVHost project\, using OSVVM’s co-simulation capabilities\, to construct an OSVVM compatible Verification Component (VC)\, used like any other VHDL based VC\, but with additional features\, to drive 3rd party PCIe IP. An example of driving Altera’s Cyclone V Hard IP for PCI Express is discussed. \nBio: Engineer with 35+ years in R&D\, with experience in ASIC design\, FPGA\, and embedded software development. Currently working on developing open-source IP in areas such as co-simulation and system modelling. A collaborator on the OSVVM project\, adding and supporting its co-simulation capabilities and developing verification IP. \nAreas of experiences include logic IP for both ASIC and FPGA\, logic verification\, HPC\, processor systems\, networking (802.3 and proprietary)\, embedded software\, co-simulation technology\, software modelling of SoC systems\, data compression logic\, PCIe endpoint design\, cellular (3G and 4G)\, wireless (802.11 and 802.15.4). Joint or sole author on several logic IP related patents. \nDetailsYassine Eben Aimine\nSiemens \n×Yassine Eben Aimine\nYassine has more than 20 years’ experience in the EDA industry. Throughout his professional career\, Yassine has partnered with design and verification engineers to deploy the latest technologies in EDA tooling in the areas of design for test\, functional verification\, and functional safety. \nDetailsPhill J Payne\nPrincipal Digital Design Engineer\nNovomorphic \n×Phill J Payne\nPhill J Payne is Principal Digital Design Engineer at Novomorphic\, specialising in secure\, real-time FPGA and embedded architectures for edge AI. He is developing convolution acceleration and a modular hardware fabric that composes reconfigurable pipelines\, reduces memory pressure\, and delivers high-performance vision and inference at the edge. Across 26 years\, Phill has turned novel architectural ideas into deployable systems under tight power\, latency\, throughput\, and reliability constraints\, with deep experience in security-grade FPGA development and signal-processing workloads. Previously\, he delivered end-to-end FPGA firmware and software for advanced systems\, including a patented communications technique designed to operate in contested jamming environments\, later acquired by a major defence prime. He also built specialised training systems used in preparation for the London 2012 Olympic Games\, translating complex engineering into practical tools. \nDetailsGavin Lofts\nField Applications Engineer\nAltera \n×Gavin Lofts\nGavin Lofts is a Field Applications Engineer at Altera with 20+ years of experience in hardware\, embedded software\, and FPGA design. He has worked on systems ranging from biosensors to radio. \nPresentation: CI/CD and Git for Modern FPGA Development
URL:https://desn.org.uk/event/verification-semiconductors-futures-conference-uk-2026/
LOCATION:University of Reading\, Whiteknights PO Box 217\, Reading\, Berkshire\, RG6 6AH\, United Kingdom
CATEGORIES:DESN Event,DESN Promoted Event
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