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DTSTART;TZID=Europe/London:20250910T100000
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DTSTAMP:20250905T095706Z
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UID:22934-1757498400-1757514600@desn.org.uk
SUMMARY:FPGA Frontrunners:  Building Resilient and Cyber Secure FPGA Systems in an Adversarial World
DESCRIPTION:REGISTERSponsored by Sundance\nEvent Overview\nIn today’s hyper-connected\, adversarial digital landscape\, the resilience and security of Field Programmable Gate Arrays (FPGAs) are no longer just engineering challenges\, they are regulatory\, legal\, and reputational imperatives. \nA system is resilient if\, and only if\, there is justifiable and enduring confidence that it will function as expected\, when expected. This is the baseline of trust in modern technology.But resilience alone is not enough. A system is secure when it can sustain this performance under direct adversarial pressure. When that adversary is remote\, persistent\, and capable of leveraging the vast cyber domain\, we call this cyber security. \nSecurity is not optional \, it is mandated by law. Increasingly\, regulatory bodies around the world are enforcing strict standards\, and the penalties for non-compliance are not limited to fines.There is a real and growing risk of parallel criminal and civil proceedings arising from the same cyber security failure\, placing immense responsibility on engineers\, designers\, and decision-makers to implement effective\, demonstrable security controls. \nThis FPGA-focused event will equip you with the knowledge\, techniques\, and assurance frameworks necessary to design systems that are not only resilient and secure—but demonstrably so. \nWho Should Attend: \n\nFPGA Designers and Engineers\nSystem Architects\nSafety and Security Specialists\nSupply Chain Professionals\nIndustry Regulators and Standards Bodies\n\nWhy Attend? \n\nGain insights from leading experts on the evolving risks and mitigation strategies\nLearn how to meet functional safety and security requirements across multiple industries\nNetwork with industry peers and potential collaborators\nParticipate in discussions on best practices\, regulatory trends\, and real-world case studies\n\nAgenda \n\n\n\n\n\nTime\nSession\n\n\n\n\n10:00\nRegistration\n\n\n10:30\nA Hardware-Accelerated Future: Pedro Machado\, Nottingham University\n\n\n11:00\nA Defence Against Remote Power Side-Channel Attack on FPGA-based CNN: Jing He\, University of Southampton\n\n\n11:30\nFPGA System and Device Level Security Considerations: Ian Pearson\, Microchip Technology Inc.\n\n\n12:00\nSecurity Risks & Controls Across the HW-to-Cloud Stack: Mike Bartley\, Alpinum Consulting\n\n\n12:15\nLunch\n\n\n13:00\nComparison of Embedded Cryptography Algorithms for an FPGA-Based Multi-Process: Jack Sampford\, Phixos\n\n\n13:30\nDesigning Reusable\, Portable and Secure IP for FPGA: Steinn Gustafsson\, Chevin Technology Limited\n\n\n14:00\nWhat do you mean Secure? Peter Davies & Sukhi Gill\, Thales\n\n\n14:30\nWrap Up\n\n\n\n\nSpeakersIan Pearson\nPrinciple Embedded Solutions Engineer\, Microchip Technology Inc. \nIan is a Principal Field Applications Engineer at Microchip Technology Inc. He has held roles in MCU and MPU applications and also led the EU Wireless team for many years introducing Wi-Fi and Bluetooth into the embedded product lines. He has been involved with IoT since it’s inception and is an advocate of enhancing security in Connected Embedded Systems. To aid this he is active on several working groups in the IoT Security Foundation and has presented on security topics at several conferences. More recently he has returned to the FPGA space and supports Microchip clients on FPGA\, SoC and Security needs across multiple market segments. \nPresentation: FPGA System and Device Level Security Considerations \nCreating a secure system is a complex task where multiple vulnerabilities in the design\, manufacture\, supply chain and maintenance of a product must be accounted for. Security is a whole of business challenge yet the foundation of a secure design relies heavily on the security capabilities of a semiconductor device and how they leverage correct implementation within the overall security posture of a product. In this presentation we will look at some of the factors involved in creating a secure FPGA\, some of the threats and mitigations and how Microchip FPGA’s implement key functionality that create devices with military grade security available to all markets. \nJing He\nDepartment of Electronics and Computer Science\, University of Southampton\nJing He is a PhD candidate in the Department of Electronics and Computer Science at the University of Southampton\, UK. He is a member of the Sustainable Electronic Technologies Group\, and his research focuses on hardware security. Specifically\, he explores lightweight\, runtime defence techniques for heterogeneous systems\, with an emphasis on protecting multi-tenant-based neural network accelerators. \nPresentation: A Defence Against Remote Power Side-Channel Attack on FPGA-based CNN \nThis talk introduces a lightweight\, runtime defence mechanism for FPGA-based deep learning accelerators against remote power side-channel attacks. By leveraging distributed convolution\, we enhance the security of CNN execution in FPGA-based environments. The session will also present recent experimental results and discuss future research challenges. \nSteinn Gustafsson\nFounder\, Chevin Technology\nSteinn Gustafsson is the founder of Chevin Technology\, a leading developer of accelerated IP for security\, data protocols\, and compute engines tailored to the defence\, aerospace\, and scientific sectors. With over 25 years of expertise in FPGA technology\, Steinn has driven innovation in communication systems\, ASIC design\, signal processing\, and digital security\, and is the holder of multiple patents. \nHe leads a highly skilled engineering team focused on delivering secure\, high-performance\, and low-latency solutions\, built for mission-critical environments. Steinn is deeply committed to technical excellence\, strategic collaboration\, and personal development\, forging partnerships that enable shared success in solving complex industry challenges. \nJack Sampford\nSenior Firmware Engineer\, Phixos\nJack is a Senior Firmware Engineer at Phixos\, with experience leading the design and implementation of multiple FPGA-based products\, primarily for space and defence applications. \nHe has worked with Phixos for the past 5 years\, providing engineering services to many industry-leading OEMs\, particularly in the domain of mission- and safety-critical FPGA designs. \nPresentation: Comparison of Embedded Cryptography Algorithms for an FPGA-Based Multi-Processor Design \nSecurity within multi-processor architectures is an increasingly important consideration\, with their recent usage within safety-critical systems highlighting the need for protection against potential attacks. These attacks can originate within the system\, such as the possibility of a malicious program being run on one of the processors which attempts to access memory belonging to another processor. Mitigation of these types of attacks can be achieved using encryption to protect data belonging to a processor\, traditionally achieved using the Advanced Encryption Standard (AES) algorithm. AES implementation on FPGA/ASIC hardware can require significant area on a device\, which is a premium resource within an embedded system. In this paper\, an alternative lightweight encryption algorithm\, eXtended Tiny Encryption Algorithm (XTEA)\, is implemented and iteratively optimised on an Altera Cyclone V FPGA as part of a multi-processor design and compared to an AES implementation in terms of throughput\, area utilisation\, and power consumption. The obtained results show that the XTEA implementation improves throughput by 48.6%\, and reduces ALM utilisation\, register utilisation\, and dynamic power consumption by 87.2%\, 85.4%\, and 86.5% respectively. This represents a significant improvement\, especially in terms of area and power consumption\, the most important metrics for the embedded multi-processor system this implementation is integrated into.
URL:https://desn.org.uk/event/building-resilient-and-cyber-secure-fpga-systems-in-an-adversarial-world/
LOCATION:Thales\, 350 Longwater Ave\, Reading\, RG2 6GF\, United Kingdom
CATEGORIES:DESN Event
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