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DTSTART;TZID=Europe/London:20250218T090000
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DTSTAMP:20250124T191208Z
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SUMMARY:FPGA FRONT RUNNER : Using AI in development and product for FPGA
DESCRIPTION:FPGA FRONT RUNNER : Using AI in development and product for FPGARegisterThe FPGA Front Runner event aims to bring together FPGA design and verification communities to discuss gate array-related topics. Participants can share knowledge\, learn about current developments\, and network with others. \nThe FPGA Front Runner event\, themed “Using AI in development and product for FPGA\,” is scheduled for Tuesday\, 18th February 2025\, from 9:00 AM to 2:00 PM at Renishaw\, UK. For more information and registration\, visit https://www.tickettailor.com/events/alpinumconsulting/1505991 \nA few speaker slots are still open for industry experts to share their insights. If you’re interested in presenting\, please contact Mike Bartley at mike.bartley@tessolve.com. \nAgenda (GMT) \n \n\n\n\n\nTime\nSpeaker\nDetails\n\n\n\n\n09.00\nArrival and registration\n\n\n\n09.30\nPete Leonard\, Renishaw\nIntroduction to Renishaw\n\n\n09.40\nGareth Richards\, AI Manager\, TechWorks\nTechWorks\n\n\n10.00\nAlexander Montgomerie Corcoran\, CEO\, Heronic\nHeronic\n\n\n10:30\nDavid Harold\, Chief Operating Officer\, RED Semiconductor\nRED Semiconductor\n\n\n11.00\nPedro Machado\, Senior Lecturer in Computer Science\, Nottingham Trent University\nNottingham Trent\n\n\n11:30\nRefreshment break\n\n\n\n12:00\nJeremy Bennett\, Embecosm\n\n\n\n12:30\nTBC\n\n\n\n13:00\nTBC\n\n\n\n13::30\nLunch\n\n\n\n14:00\nClose\n\n\n\n\n\n\nPrior to the main event\, we are pleased to offer a pre-event overview showcasing the key areas of discussion on Tuesday\, 21st Jan 2025. We kindly request your attendance for a 30-minute preview.
URL:https://desn.org.uk/event/fpga-front-runner-using-ai-in-development-and-product-for-fpga/
LOCATION:Renishaw\, Wotton-Under-Edge\, GL12 8JR\, United Kingdom
CATEGORIES:DESN Event
ATTACH;FMTTYPE=image/jpeg:https://desn.org.uk/wp-content/uploads/2024/12/FPGA-FRONTRUNNER-5.jpg
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